71m6534h-igt Maxim Integrated Products, Inc., 71m6534h-igt Datasheet - Page 51

• Manufacturer Part Number: 71m6534h-igt
• Description: Energy Meter Ic
• Manufacturer: Maxim Integrated Products, Inc.

FDS_6533_6534_004
1.4.12 Hardware Watchdog Timer
An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6533/71M6534. It
uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least
every 1.5 seconds. When not refreshed on time, the WDT overflows and the part is reset as if the RESET
Figure 16: Functions defined by V1
The watchdog timer is also reset when the internal signal WAKE=0 (see Section
If enabled with the IEN_WD_NROVF register in I/O RAM, an interrupt occurs roughly 1 ms before the WDT
resets the chip. This can be used to determine the cause of a WDT reset since it allows the code to log
its state (e.g. the current PC value, loop counters, flags, etc.) before a WDT reset occurs.
1.4.13 Test Ports (TMUXOUT Pin)
One of the digital or analog signals listed in
The function of the multiplexer is controlled with the I/O RAM register TMUX (0x20AA[4:0]), as shown in
Table
The TMUXOUT pin may be used for diagnosis purposes or in production test. The RTC 1-second output
may be used to calibrate the crystal oscillator. The RTC 4-second output provides even higher precision.
v1.1
V3P3 - 10mV
V3P3 -
400mV
VBIAS
V3P3
44.
0V
V1
operation,
enabled
Normal
Battery
WDT dis-
modes
WDT
abled
© 2007-2009 TERIDIAN Semiconductor Corporation
pin were pulled high, except that the I/O RAM bits will be in the same
state as after a wake-up from SLEEP or LCD modes (see the I/O RAM
description in
wake-up). 4100 oscillator cycles (or 125 ms) after the WDT overflow, the
MPU will be launched from program address 0x0000.
A status bit, WD_OVF, is set when the WDT overflow occurs. This bit is
powered by the nonvolatile supply and can be read by the MPU when
WAKE rises to determine if the part is initializing after a WDT overflow
event or after a power-up. After it is read, the MPU firmware must clear
WD_OVF. The WD_OVF bit is also cleared by the RESET pin.
There is no internal digital state that deactivates the WDT. The WDT can
be disabled by tying the V1 pin to V3P3 (see
also deactivates V1 power fault detection. Since there is no method in
firmware to disable the crystal oscillator or the WDT, it is guaranteed that
whatever state the part might find itself in, upon watchdog overflow, the
part will be reset to a known state.
Asserting ICE_E will also deactivate the WDT. This is the only method
that will work in BROWNOUT mode. In normal operation, the WDT is re-
set by periodically writing a one to the WDT_RST bit.
Table 44
Section 4.2
can be selected to be output on the TMUXOUT pin.
for a list of I/O RAM bit states after RESET and
71M6533/71M6534 Data Sheet
Figure
2.5 Wake Up
16). Of course, this
Behavior).
51