le79128 Zarlink Semiconductor, le79128 Datasheet - Page 17

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

VCP Direct Page Hardware Register Summary
Table 10
Interrupt Indication
Interrupt Parameter
Page Offset
Mailbox Flag
Page 255 Checksum (High)
Page 255 Checksum (Low)
Page 255 Base Address
(High)
Page 255 Base Address
(Low)
PCLKB Select
PCLKA Select
Clock Status
MCLK Configuration
System Real Time Status
System Interrupt Mask
Boot Sense (High)
Boot Sense (Low)
Reset Type
Entry Address (High)
Entry Address (Low)
Register Name
Table 10. VoiceEdge™ VCP Hardware Derived Register Space
provides an overview listing of the hardware derived registers. These registers reside on the Direct Page.
INTIND
INTPARAM
PGOFFSET
MBFLAG
CHKSUM
BASE_ADDR
PCLKB_SEL
PCLKA_SEL
CLKSTAT
MCLKCONFIG
SYSSTAT
SYSMASK
ENT_ADDR
Mnemonic
Microsemi Corporation - CMPG
Used by VpGetEvent() to get the next event
from the queue.
Used by VpGetEvent() to get the next
event’s parameter.
Allows for interleaved page accesses. Not
used by the VP-API.
Used by the VCP firmware and VP-API to
provide page handshaking.
Checksum of Boot Load data.
Used for Boot Load.
PCLK A and B Select Register: VCP defaults
to autodetect the PCLK rate.
System Clock status
Reference Clock configuration
System Interrupt (fault) status.
System Interrupt (fault) mask.
Boot sense value. It contains the steady state
(pulled up or down) values of each GPIO pin
as sensed by the Boot Loader.
A 4-bit value indicating the cause of the last
System Reset event.
Program entry address for an HBI-loaded
application. The host application image will
write this register before writing the Software
Flags register to launch the application
correctly.
Le79128
Register Description
17
Preliminary Data Sheet
Offset
0x0A
0x0B
0x0C
0x0D
0x00
0x01
0x02
0x03
0x04
0x06
0x07
0x08
0x14
0x15
0x16
0x18
0x19
0x05
0x09
These registers
are updated by
firmware some
time after reset
Notes