le79128 Zarlink Semiconductor, le79128 Datasheet - Page 21

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

AUTO_HIWAYBA
FSB_GEN
PCLKB_FREQ[12:0]:
Using FSB as an 8-kHz reference, the device will automatically select the correct PCLKB_FREQ
value. The initial PCLKB_FREQ[12:0] setting will be 1001011111011 (PCLKB=38.880 MHz). If the
FSB or PCLKB pulses are absent, the device will maintain CSEL[12:0] = 1001011111011 until it
detects transitions on both the FSB and PCLKB inputs. Automatic frequency detection will occur
after 9 consistent FSB periods. Meaning, reading this register before the mentioned 1.125 ms will
report the default (0x92FB) PCLKB, not the actual PCLKB frequency.
If FSB is to be generated internally, set FSB_GEN bit to internal generation, set the
AUTODETECTB bit to 0 and write the appropriate clock frequency register PCLKB_FREQ[12:0]
with the desired value. This can be done in the Hardware Abstraction Layer (HAL) function used to
initialize the chip and configure the HBI interface. This should be done before booting the device.
PCLKA Select (PCLKA_SEL)
PCLKA_SEL is used to configure the PCLKA input to the VCP, depending on the relationship
between FSA (frame sync) and PCLKA.
AUTODETECTA
DETECTA
AUTO-
D15
D7
HIWAYAB
AUTO_
D14
D6
Indicates the set frequency of PCLKB as a multiple of 8KHz -1. When
Redundant Highway to Highway A Switch.
0: Disable highway automatic switching option.
1: Automatically switch from Redundant Highway to Highway A if
FSB Generation.
0: FSB is provided externally.
1: FSB is generated by the VCP device at the specified frequency. Whenever this
writing AUTODETECTB = 1, the default is restored to these bits
1001011111011 until the auto-detection is complete. PCLKB can be any
frequency that is a multiple of 512KHz +/- 6000ppm. The software
supports PCLK frequencies up to 8.192 MHz.
0000000111111:
0000010111111:
0000011111111:
0000111111111:
0001111111111:
0011111111111:
1000100111111:
1001011111011:
Highway A Auto Detect.
0: Autodetect disabled. PCLKA_FREQ[12:0] should be set by the user.
1: Autodetect the frequency of PCLKA based on the FSA period and store result
PCLKB_FREQ field is initialized (default)
CFAIL_PCLKB=1 and CFAIL_PCLKA=0 (See CLKGEN_STATUS for definition
of CFAIL_PCLK)
bit is set to High, the AUTODETECTB bit should be set to low by the host soft-
ware.
FSA_GEN
in PCLKA_FREQ[12:0]. When High, the auto detection is restarted and the
PCLKA_FREQ field is initialized (default).
Microsemi Corporation - CMPG
D13
D5
Le79128
21
D12
PCLKA_FREQ[7:0]
D4
PCLKB = 512 kHz.
PCLKB = 1.536 MHz
PCLKB = 2.048 MHz.
PCLKB = 4.096 MHz.
PCLKB = 8.192 MHz.
PCLKB = 16.384 MHz.
PCLKB = 35.328 MHz ADSL clock
PCLKB = 38.880 MHz (default)
D11
D3
PCLKA_FREQ[12:8]
Direct page address 0x09 (RW)
D10
D2
Preliminary Data Sheet
D9
D1
D8
D0