le79128 Zarlink Semiconductor, le79128 Datasheet - Page 20

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

Page 255 Checksum Low Register
This double-word register holds the checksum for any boot operation. The code load integrity is
guaranteed by the checksum hardware which resides in this register. This register is used by the
VP-API to verify the integrity of a boot load operation.
Page 255 Base Address High Register (BASE255)
Page 255 Base Address Low Register (BASE255)
This double-word register is used for code loading. The API uses this register accordingly. The host
software needs no further manipulation of this register.
BASE_ADDR[31:8]
RESET: (Read only)
Note: This Page 255 Base Low Register can be polled immediately after RST is deasserted high or power is
PCLKB Select (PCLKB_SEL)
PCLKB_SEL is used to configure the PCLKB input to the VCP, depending on the relationship
between FSB (frame sync) and PCLKB.
AUTODETECTB
applied to determine when internal chip reset is complete. No other register should be read or written during
this time. This register will return 0xFF01 until reset is complete at which time 0xFF00 is returned.
DETECTB
AUTO-
RSVD
D15
D15
D15
D15
D7
D7
D7
D7
HIWAYBA
RSVD
AUTO
D14
D14
D14
D14
D6
D6
D6
D6
Upper address bits of Page 255 accesses.
This bit can be polled to indicate when the internal chip reset is complete.
Auto-detected Redundant Highway.
0: Autodetect disabled. PCLKB_FREQ[12:0] should be set by the user.
1: Autodetect the frequency of PCLKB based on the FSB period and store result
FSB_GEN
in PCLKB_FREQ[12:0]. When high the auto detection is restarted and the
Microsemi Corporation - CMPG
D13
D13
D13
D5
D5
D5
D13
D5
Le79128
20
RSVD
BASE_ADDR[23:16]
D12
D12
D12
BASE_ADDR[15:8]
D4
D4
D4
PCLKB_FREQ[7:0]
D12
D4
CHKSUM[15:8]
CHKSUM[7:0]
BASE_ADDR[29:24]
D11
D11
D11
D3
D3
D3
D11
D3
PCLKB_FREQ[12:8]
Direct page address 0x08 (RW)
Direct page address 0x06 (RW)
Direct page address 0x07 (RW)
Direct page address 0x05 (RW)
D10
D10
D10
D10
D2
D2
D2
D2
Preliminary Data Sheet
D9
D1
D9
D1
D9
D1
D9
D1
RESET
D8
D0
D8
D0
D8
D0
D8
D0