le79128 Zarlink Semiconductor, le79128 Datasheet - Page 26

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

Code Loading
The VCP device will always come up in Boot mode following a power-on reset or when the reset pin of the chip is deasserted.
The DSP will delay program execution until the boot sequence is completed as defined by the pin strapping. The VCP device
contains an on-chip ROM with initial startup code, a simple ROM monitor, and a boot loader. Before the ROM monitor runs, initial
startup code is run to perform system diagnostics. The diagnostics consist of evaluating the GPIO[31:24] boot strap pins, testing
for a stable system clock and testing/repairing the device’s internal RAM if so configured. The evaluation of the GPIO[31:24] is
accomplished by a crude software delay of at least 200 µs, and then polling the state of those pins. The clock failure may take
significant time to disappear due to waiting for autodetection or a host write.
Host Boot Procedure
The download code will be composed of a sequence of words that must be presented to the device via the GPI/SPI. These images
can be broken up at 128-byte boundaries if needed. The first byte of the sequence (or after a break in the sequence of 128 blocks)
must have the PADDR signal asserted. Any Microsemi provided image will conclude with the Page 255 Checksum register
returning the value AA55 AA55. This register should be verified by the Host before proceeding.
GPIO[31]/MCS15
GPIO[30]/MCS14
GPIO[29]/MCS13
GPIO[28]/MCS12
GPIO[26]/MCS10
GPIO[27]/MCS11
GPIO[25]/MCS9
GPIO[24]/MCS8
Pin
Table 12. Boot Sense Pin Definitions
Entry Address High Register
Entry Address Low Register
Program entry address for an HBI-loaded application. The host application image will write this
double-word register before writing the Software Flags register to launch the application correctly.
D15
D15
D7
D7
Boot Sense Function
GPIO_MESSAGES
UART_ENABLE
D14
D14
SLOW_SPEED
BIST_DISABLE
BOOT_DEBUG
D6
D6
CFAIL_SKIP
RSVD
RSVD
Microsemi Corporation - CMPG
D13
D13
D5
D5
Le79128
0: Write the PLL to the maximum frequency(140MHz).
1: Do not adjust the PLLDIV field(98.304MHz).
0: Wait for CFAIL before proceeding with BOOT routine.
1: Do not wait for CFAIL before proceeding.
0: Enable Memory BIST/Repair in BOOT routine.
1: Disable Memory BIST/Repair in BOOT routine.
0: Do not enter debug mode.
1: Enter debug mode after Memory BIST if enabled.
0: Disable UART CLI during booting.
1: Enable UART CLI during booting.
0: Disable GPIO messages during booting.
1: Enable GPIO messages during booting.
26
D12
D12
ENT_ADDR [31:24]
ENT_ADDR [23:16]
D4
D4
ENT_ADDR [15:8]
ENT_ADDR [7:0]
D11
D11
D3
D3
Description
Direct page address 0x18 (RW)
Direct page address 0x19 (RW)
D10
D10
D2
D2
Preliminary Data Sheet
D9
D1
D9
D1
D8
D0
D8
D0