le79128 Zarlink Semiconductor, le79128 Datasheet - Page 40

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le79128

Manufacturer Part Number
le79128
Description
Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
Manufacturer
Zarlink Semiconductor
Datasheet
Notes:
1.
2.
3.
4.
5.
6.
Refer to Figure 26 for timing diagram test points.
SCK may be stopped in the High or Low state indefinitely without loss of information. When SS is at Low state, every 16 SCK cycles the 16-
bit received data will be interpreted by the SPI interface logic.
The first data bit is enabled on the falling edge of SS or on the falling edge of SCK, whichever occurs last.
The SPI slave requires 61ns SS Off time just to make the transition of SS synchronized with SCK clock. In the command framing mode,
there is no SS Off time between each 16-bit command/data and SS is held low until the end of command.
If SS is not held Low for 16 or 8 SCK cycles exactly, the SPI slave will reset. During byte or word framing mode, SS is held Low for 8 or 16
SCK cycles. During command framing mode, SS is held Low for the whole duration of the command. Besides, multiple commands can be
transferred with SS low for the whole duration of the multiple commands. The rising edge of the SS indicates the end of the command
sequence and resets the SPI slave.
Pin loading is assumed to be C
Table 18. SPI Timing Parameters
No.
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
Symbol
t
t
t
t
t
t
t
t
t
ODOF
t
t
t
t
ICSS
ICSH
ICSO
t
t
DCY
DCH
DCR
ICSL
ODD
ODH
ODC
DCL
DCF
IDH
IDS
load
Serial clock period
Serial clock HIGH pulse width
Serial clock LOW pulse width
Rise time of clock
Fall time of clock
Slave select setup time
Slave select hold time
Slave select pulse width
Slave select off time
Input data setup time
Input data hold time
Output data turn on delay
Output data hold time
Output data turn off delay
Output data valid
= 75pF
1
Parameter
Microsemi Corporation - CMPG
Le79128
40
Min
61
10
24
11
61
14
2
2
2
0
2
Typ
Preliminary Data Sheet
t
t
t
t
DCY
DCY
DCY
DCY
Max
15
10
15
8
8
–15
–15
–15
–15
Unit
ns
Note
3, 6
2,4
6
2
2
5
6
6

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