80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 103

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
8.5.1 Key to the Flag Registers
masked and are enabled by unmasking the bits.
Note:
The flag registers are listed in the order of priority for doorbells and interrupts. All masks power up and reset to fully
All flag register tables are shown with the following column headings and symbols within the register:
#
7-0
8
9
11-10
15-12
23-16
31-24
39-32
47-40
55-48
63-56
7:0)
8)
9)
11:10)
15:12)
23:16)
31:24)
39:32)
47:40)
55:48)
63:56)
#:
Signal:
Stat:
–
–
RW:
Signal
FLAGS
TT
WR32
PRIO
RES
DESTID
DESTID
MASK
RES
MASK
MASK
These 8 bits within the register are where the flags are stored. As noted below, there is a name, a status
for the flag and a description of the flag shown for each flag. Some flags are updated real time, while
others latch and must be cleared.
Designates whether source and destination IDs of the doorbell should use 8 bits or 16 bits. The true TT is
two bits, but only one bit is required to make 8/16 designation.
Wr32 designates whether a write to this register is 8 bits or 32 bits. An 8 bit write would write a mask to
the flag portion of the register to clear the masked flags. Within the mask, any flag that is overwritten by
“1” would be cleared. Any flag overwritten with a “0” would be unaffected by the write. A 32 bit write to this
register would be required to alter the destination ID and TT portions of the register. In a 32 bit write, the
flags could be cleared or left unaffected, based upon the state of the 8 LSBs of the write, the same as
with the 8 bit write. Note that RT flags cannot be cleared.
These bits indicate the priority that should be used for any sRIO doorbell packet.
Any unused bits are indicated as Reserved.
This is the 8 bit destination ID for a doorbell on S-Port if the mask bits 8-15 allow a doorbell to be created.
This is the 16 bit extension to the destination ID for doorbells on S-Port if using sRIO extended
addresses.
These are the mask bits for the flags. Any unmasked flag will cause a doorbell to be sent on S-Port.
Reserved for future use.
This is the mask for the Int 0 interrupt pin.
This is the mask for the Int 1 interrupt pin.
CL:
RT:
possible
The bit location within the designated register
Indicates whether the flag may be cleared
Used with masks to indicate the bits are Read/Write through a configuration read/write
An abbreviated name for the Flag
Clearable flag. These flags will latch upon toggling and must be cleared by a write to the register
Indicates the flag is a real time and always represents current conditions. Clearing a RT flag is not
Stat
X
RW
RW
RW
X
RW
RW
RW
X
RW
RW
Description
There are up to 8 flags contained in the register
Defines whether the sRIO doorbell is an 8 or 16 bit destination ID
0 = Write 8 bits (clear flags only), 1 = Write 32 bits (write new dest IDs)
Priority for Doorbell packet
Unused bits
Destination ID for sRIO Doorbell
Destination ID for sRIO Doorbell, for 16 bit extension
S-Port Doorbell Mask
Unused bits
Interrupt 0 Mask
Interrupt 1 Mask
103 of 172
Table 85 Flag and Flag Mask Register
Advanced Datasheet*
March 19, 2007