80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 68

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
8.1.5 Command and Status Registers
control and determine the status of its internal hardware. All registers are 32 bits wide and are organized and accessed in
the same way as the CARs.
reserved registers and register bits.
Processing Element Logical Layer Control CSR
Local Configuration Space Base Address 1 CSR
local physical address double-word offset for the processing element’s configuration register space, allowing the configura-
tion register space to be physically mapped in the processing element. This register allows configuration and maintenance
Note:
Note:
Name:
The SerB contains a set of Command and Status Registers (CSRs) that allows an external processing element to
Refer to Table 5-2 of the RIO Input/Output Logical Specification in Chapter 5 for the required behavior for accesses to
PELLCCSR controls the extended addressing abilities. SerB will only support 34-bit addressing.
PELLCCSR is a read only register.
The local configuration space base address 1 command and status register specifies the least significant bits of the
11
12
13
14
15
31:16
2:0
31:3
Bit
Bit
1.
1.
PROC_ELMT_CTRL_CSRAddress:
The above register is described in the RIO Specification Part 1, sec. 5.4.8, Part 2, sec. 5.4.2, Part 5, sec. 5.4.2,
Part 10, sec. 5.4.2
The above register is described in the RIO Specification Part 1, sec. 5.5.1
DATA_MSG
NWR_W_RESP
STRM_WR
NWRITE
NREAD
-
EXT_ADDR_CTRL
-
Field Name
Field Name
Table 20 Processing Element Logical Layer Control CSR
1b0
1b1
1b1
1b1
1b1
0
3b001
0
Reset
Value
Reset
Value
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Table 19 Destination Operations CAR
Data Message:
PE can support a data message operation.
NWRITE_R:
PE support a Nwrite_R operation.
Streaming Write:
PE support an Swrite operation.
NWRITE:
PE support a Nwrite operation.
NREAD:
PE support a Nread operation.
Reserved.
Extended Addressing Control (read-only):
Controls the number of address bits generated by the PE as a
source and processed by the PE as the target of an operation.
3b100 - PE supports 66 bit addresses
3b010 - PE supports 50 bit addresses
3b001 - PE supports 34 bit addresses (default)
All other encoding reserved.
Reserved.
0x00004C
Comment
Comment
Advanced Datasheet*
March 19, 2007