80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 157

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
W15
Y4
Y16
AA5
AA10
AA15
AB4
A6
B6
A7
B7
D6
C8
D8
C10
C11
C12
U2
AA1
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
IDS
IRQ0
SERDES
Ground
(CMOS)
SERDES
Ground
(CMOS)
SERDES
Ground
(CMOS)
SERDES
Ground
(CMOS)
SERDES
Ground
(CMOS)
SERDES
Ground
(CMOS)
SERDES
Ground
(CMOS)
I
I
I
I
I
I
I
I
I
I
ID Select
Interrupt 0
2
2
2
2
2
2
2
2
2
2
C
C
C
C
C
C
C
C
C
C
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD3, GND) / CMOS Output
157 of 172
Analog GND for TX/RX pairs. All pins must be tied to single
potential ground plane.
Analog GND for TX/RX pairs. All pins must be tied to single
potential ground plane.
Analog GND for TX/RX pairs. All pins must be tied to single
potential ground plane.
Analog GND for TX/RX pairs. All pins must be tied to single
potential ground plane.
Analog GND for TX/RX pairs. All pins must be tied to single
potential ground plane.
Analog GND for TX/RX pairs. All pins must be tied to single
potential ground plane.
Analog GND for TX/RX pairs. All pins must be tied to single
potential ground plane.
I
GND at power-up. NOTE: SUPPLY / LEVELS REQUIREMENTS
ARE UNQUE FROM THE OTHER I
I
GND at power-up.
I
GND at power-up.
I
GND at power-up.
I
GND at power-up.
I
GND at power-up.
I
GND at power-up.
I
GND at power-up.
I
GND at power-up.
I
GND at power-up.
sRIO 8/16 bit Destination ID Select
This is an interrupt output pin whose value is given by the Error
Management Block.
2
2
2
2
2
2
2
2
2
2
C Slave ID address bit 0. This should be set statically to Vdd or
C Slave ID address bit 1. This should be set statically to Vdd or
C Slave ID address bit 2. This should be set statically to Vdd or
C Slave ID address bit 3. This should be set statically to Vdd or
C Slave ID address bit 4. This should be set statically to Vdd or
C Slave ID address bit 5. This should be set statically to Vdd or
C Slave ID address bit 6. This should be set statically to Vdd or
C Slave ID address bit 8. This should be set statically to Vdd or
C Slave ID address bit 7. This should be set statically to Vdd or
C Slave ID address bit 9. This should be set statically to Vdd or
Advanced Datasheet*
2
C PINS.
March 19, 2007