80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 98

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
Memory Address Increment Register
Memory Stop Address Register
8.2.14 Packet Interval Timer Register
problem, both the data packets and the doorbells exiting S-Port 1 may be timed with a programmable interval timer. The
interval timer uses the PHY clock 156.25MHz as the tick. A set interval is programmed into the PPS Packet Interval Timer
Register. When a packet is sent using sRIO out S-Port 1, the interval timer will begin counting down, starting when the
packet has completed. When the counter reaches zero, a following packet may be sent. The PPS acceptance of doorbells
is much faster than data packets: therefore, they will be accomplished by a second counter with the countdown initiated
when the doorbell starts.
Data Packet Interval Timer Register
Note:
Name:
Name:
Name:
The PPS has no storage capability and cannot accept packets faster that its processing capability. To solve this
Bit
30:0
31
Bit
5:0
31:6
Bit
30:0
31
1.
CNT_MEM_ADDR
MEM_ADDR_MEM
MEM_STOP_ADDR
stop address to be missed.
The stop address must align with the start address and the address increment. A misalignment may cause the
Field Name
CNT_MEM_ADDR
-
Field Name
MEM_ADDR_INC
-
Field Name
MEM_STOP_ADDR RW
-
Table 71 Missing Packet Address Increment Register
Type
RW
Type
RW
Type
Table 70 Missing Packet Current Address Register
Table 72 Missing Packet Stop Address Register
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Address:
Address:
Address:
Reset
Value
31h0
0
Reset
Value
6h0
0
Reset
Value
31h0
0
0x18584
0x18588
0x1858C
Comment
Current Memory Address:
Used to hold the current memory address
Reserved
Comment
Memory Address Increment:
Used to predict next current memory address
Reserved
Comment
Memory Stop Address:
The last allowed memory address
Reserved
Advanced Datasheet*
March 19, 2007