80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 158

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Y1
A11
B11
B3
Y17
B10
P18
R18
P19
R19
T21
U21
T22
U22
N19
N18
R22
R21
P22
P21
N22
N21
IRQ1
MBDONE
MBPASS
MRST_N
PLL_OFF
PPE_N
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Interrupt 1
Memory BIST
Memory BIST
Master Reset
PLL Off
Parallel Port
Enable
QDR SRAM
Data Out 0
QDR SRAM
Data Out 1
QDR SRAM
Data Out 2
QDR SRAM
Data Out 3
QDR SRAM
Data Out 4
QDR SRAM
Data Out 5
QDR SRAM
Data Out 6
QDR SRAM
Data Out 7
QDR SRAM
Data Out 8
QDR SRAM
Data Out 9
QDR SRAM
Data Out 10
QDR SRAM
Data Out 11
QDR SRAM
Data Out 12
QDR SRAM
Data Out 13
QDR SRAM
Data Out 14
QDR SRAM
Data Out 15
(VDD3, GND) / CMOS Output
(VDD, GND) / CMOS Output
(VDD, GND) / CMOS Output
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
158 of 172
This is an interrupt output pin whose value is given by the Error
Management Block.
MBIST Done. Set (MBDONE = 1) when MBIST patterns are com-
pleted
MBIST Pass. Set (MBPASS = 1) when MBIST patterns pass.
Cleared (MBPASS = 0) and is sticky when MBIST fails.
SerB Global Reset. Sets all internal registers to default values.
Resets all PLLs. Resets all port configurations. This is a HARD
Reset.
Used for device testing with PLL bypass.
PPE = 0, P-Port is active
PPE = 1, P-Port is powered down and not used (low power).
The QDR Output Data Bus 0
The QDR Output Data Bus 1
The QDR Output Data Bus 2
The QDR Output Data Bus 3
The QDR Output Data Bus 4
The QDR Output Data Bus 5
The QDR Output Data Bus 6
The QDR Output Data Bus 7
The QDR Output Data Bus 8
The QDR Output Data Bus 9
The QDR Output Data Bus 10
The QDR Output Data Bus 11
The QDR Output Data Bus 12
The QDR Output Data Bus 13
The QDR Output Data Bus 14
The QDR Output Data Bus 15
Advanced Datasheet*
March 19, 2007