80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 93

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
8.2.9 MBIST Control Register
clear on read on most bits. It is expected that all BIST will be controlled by one location/Port, preventing conflicts that may
develop from interacting ports, making the clear on read a valid operational mode.
8.2.10 QBIST Control Register
Note:
Note:
Name:
The MBIST is the primary method for memory testing. The MBIST register is one of the few configuration registers with
The QBIST accompanies the MBIST register. Most bits are clear on read.
Bit
0
1
2
7:3
15:8
20:16
21
22
23
24
25
31:26
1.
2.
3.
1.
a.
b.
c.
CONFIG_REG_MBIST
as soon as it has arrived and been accepted, the watermark should be set to zero.
Word count.
becomes 1), after that, bit 1 will be self cleared to 0.
The watermark is the trigger point at which the flag will be set. As a master that will always transmit new data
D-Word or Packet count indicates whether the watermark and waterlevel are in terms of packet count or in D-
Flush or Single Packet determines what happens when data is sent out of the queue.
MBIST will start when bit 1 is 1, and bit 0 changes from 0 to 1. Bit 1 will stay at "1" till MBIST is done (bit 24
Field Name
MBIST_START
MBIST_EN
I2C_MEM_EN
-
MBIST_MEM_ERR
-
MB_P1_SR_ME
MB_P2_PP_ME
-
MB_DONE
MB_PASS
-
On flush, all data in the queue is transmitted, except for new data that arrives during the flush.
On Single Packet, only enough data is sent to lower the waterlevel below the watermark. Presumably, in
most situations, this will be a single packet or D-Word.
It should be noted that the Flush or Single Packet works with the Master/Slave selection in the
Configuration Register
the waterlevel triggers a flag only and the queue may then be read.
Type
RW
RW
RW
RT
RT
RT
RT
RT
. If the queue is a master, the waterlevel triggers the data transmission. If a slave,
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Address:
Table 61 MBIST Control Register
Reset
Value
1b0
1b0
1b0
0
8h0
0
1b0
1b0
0
1b0
1b1
0
0x180C8
Comment
Memory BIST Start:
This bit self clears after MBIST is complete
Memory BIST Enable:
This bit is read/write, must stay high during MBIST
I
Bits 1 and 2 are XOR
Reserved
Memory BIST Main Memory Block Error:
Block 7 - 0
Reserved
Memory BIST Port 1 / sRIO Memory Error
Memory BIST Port 2 / Parallel Port Memory Error
Reserved
Memory BIST Done:
If this bit is not “1”, the flags from 8 -25 will not clear on read
Memory BIST Pass
This bit is meaningful only when bit 24 = 1
Reserved
2
C Memory Access Enable:
Advanced Datasheet*
March 19, 2007
Serial Port