80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 72

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
1x/4x LP-Serial Register Block Header
Error Management) and the EF_ID that identifies this as the generic end point port maintenance block header. Note that
while registers defined by software assisted error recovery are supported, software assisted error recovery is not (these
registers are included for hot insertion only); therefore, RIO is defined here as not supporting software assisted error
recovery. PMBH0CSR is a read-only register.
Port Link Time-out Control CSR
events such as sending a packet to receiving the corresponding acknowledge and sending a link-request to receiving the
corresponding link-response. The reset value is the maximum time-out interval, and represents between 3 and
Port Response Time-out Control CSR
for sending a request packet to receiving the corresponding response packet. The reset value is the maximum time-out
interval, and represents between 3 and 5 seconds.
Note:
Note:
Name:
Name:
Name:
The port maintenance block header 0 register contains the EF_PTR to the next EF_BLK (Extended Features Space,
The port link time-out control register contains the time-out timer value for all ports on a device. This time-out is for link
The port response time-out control register contains the time-out timer count for all ports on a device. This time-out is
7:0
31:8
7:0
31:8
15:0
31:16
Bit
Bit
Bit
1.
1.
PORT_MAINT_BLK_HDRAddress:
PORT_LNK_TO_CTRL_CSRAddress:
PORT_RESP_TO_CTRL_CSRAddress:0x000124
The above register is described in the RIO Specification Part 6, sec. 6.6.2.1
The above register is described in the RIO Specification Part 6, sec. 6.6.2.2
-
PORT_LINK_VAL
-
PORT_RESP_VAL
EF_ID
EF_PTR
Field Name
Field Name
Field Name
0
0xFFFFFF
0
0xFFFFFF
0x0001
0x0600
Table 26 1x/4x LP-Serial Register Block Header
Reset
Value
Reset
Value
Reset
Value
72 of 172
Table 28 Port Response Time-out CSR
Table 27 Port Link Time-out CSR
Extended Features ID:
Hard wired extended features ID, Generic End Point Devices.
Extended Features Pointer:
Hard wired pointer to the next block in the data structure.
Reserved.
Port Link Time-out Internal Value:
Setting to all 0’s disables the link time-out timer. This value is loaded
each time the link time-out timer starts.
Reserved.
Port Response Time-out Internal Value:
Setting to all 0’s disables the link time-out timer. This value is loaded
each time the link time-out timer starts.
0x000100
0x000120
Comment
Comment
Comment
Advanced Datasheet*
March 19, 2007
5
seconds.