txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 15

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

OTHER PINS
Symbol
DROPT
ENABT
AISCK
EXAIS
ISTAT
PAIS
STAI
Pin No.
36
35
37
38
71
17
39
I/O/P
I
I
I
I
I
I
I
CMOS
TTLp
Type
TTL
TTL
TTL
TTL
TTL
Enable Add Bus Timing: Works in conjunction with the
DROPT lead. The following table is the definition of the timing
modes:
ENABT
Drop Timing Mode Enabled: Works in conjunction with the
ENABT lead. See table above.
External STS Alarm Indication: The purpose of this lead is to
provide an upstream AIS indication for the L4M. This pin is
enabled by writing a 1 to the EAPE control bit. A high on this
lead generates AIS, and path RDI, when enabled.
External Path AIS Indication: The purpose of this lead is to
provide an upstream AIS indication for the L4M. This pin is
enabled by writing a 1 to the EAPE control bit. A high generates
line AIS, and path RDI, when enabled.
STS Network Alarm Indication: This pin is enabled by writing
a 1 to the XRDIEN control bit. A high generates a path RDI,
when enabled.
AIS Clock Input: Enabled when control bit BSAISE is a 0. This
clock is used to generate transmit and receive 140 Mbit/s AIS
on defined alarms. The clock frequency must be 34.816 MHz
+/- 15 ppm for a nibble interface, and 17.408 MHz +/- 15 ppm
for a byte interface. If AIS bit stuffing is used to generate AIS
(control bit BSAISE is written with a 0), this clock is not
required.
External AIS Alarm Input: A low causes a receive 140 Mbit/s
AIS when enabled, and a path RDI to be generated. May be
used when processing received POH bytes via external cir-
cuitry (e.g., C2 byte).
1
0
0
DATA SHEET
- 15 -
DROPT
X
0
1
External timing. Add bus timing derived
from the external clock (EXTC) and the
external framing pulse (EXC1). The
ASPE, AC1J1, ACLK and AC1 signal
leads become output leads.
Add bus timing. Data derived from the
add bus clock, ASPE, and AC1J1 input
signals. Note: ASPE, AC1J1, AC1 and
ACLK are inputs.
Drop bus timing. Data, ASPE, AC1J1,
and ACLK output signals are derived
from the drop bus clock (DCLK) and C1
pulse in the drop bus DC1J1 signal.
Name/Function
Action
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M