txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 9

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

SDH/SONET DROP BUS INTERFACE
Symbol
(n=7-0)
DC1J1
DPAR
DSPE
DCLK
DDn
DC1
141-137
135-133
Pin No.
131
128
127
129
126
I/O/P
I
I
I
I
I
I
Type
TTL
TTL
TTL
TTL
TTL
TTL
Drop Bus Clock: Byte-wide data (DD7-DD0), parity (DPAR),
payload indicator (DSPE), and the C1 and J1 pulses (DC1J1)
are clocked into the L4M on negative transitions of this clock,
which has a rate of 19.44 MHz. The clock signal is used for
receive timing, and is monitored for loss of clock.
Drop Bus Parity Bit: This input represents an odd parity cal-
culation for each data byte, the DSPE signal, and the DC1J1
signal. When the internal pointer tracking feature is enabled,
parity is calculated for data and the C1 pulse only. When a 1 is
written to control bit PARDO, parity is calculated for the data
byte only.
Drop Bus C1J1 Indicator: The C1 pulse is an active high,
one clock cycle wide timing pulse, that indicates the starting
location of the first C1 byte time slot in the STM-1 or STS-3c
frame when DSPE is low. When the pointer tracking feature is
disabled, a J1 pulse, also one clock cycle wide, must be
present to identify the starting location of the J1 byte in the
AU-4 VC-4, or in the STS-3c SPE signal when DSPE is high. If
the J1 pulse is not present, the pointer tracking feature must
be enabled. The C1 pulse must be provided on this signal
lead, or on the DC1 signal lead. Up to a frame in offset delay
for the C1 byte can be compensated for when the pointer
tracking mode is enabled. The receive offset delay is con-
trolled by bit RC1DC in the memory map.
Drop Bus SPE Indicator: A signal that is active high during
the AU-4/STS-3c SPE time when the pointer tracking feature is
disabled. This signal is not required when the pointer tracking
feature is enabled.
Drop Bus Byte: Byte-wide data that corresponds to the AU-4/
STS-3c signal from the drop bus. The first bit dropped corre-
sponds to DD7 (pin 141).
Drop Bus C1 Pulse: An external positive C1 pulse that may
be provided on this pin instead of in the DC1J1 signal. This
signal is or-gated internally with the DC1J1 signal to form a
composite C1J1. When this signal lead is not used, it must be
grounded.
DATA SHEET
- 9 -
Name/Function
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M