txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 80

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

Address
22
23
Bit
7
6
5
4
3
2
1
BUSERR Received Parity Error Detected: An alarm indicates that a parity error has
PSLERR Path Signal Label Mismatch Detected: An alarm indicates that the
Symbol
RFIFOE
C2EQ0
J1LOL
J1TIM
RRDI
been detected in the drop bus signals. The drop bus data, SPE signal and
composite C1J1 pulse are calculated for odd parity and compared against
the parity bit input for parity errors when the pointer tracking feature is dis-
abled (PTEN lead is low). The drop bus data, and C1 pulse is calculated for
odd parity and compared against the parity bit input for parity errors when
the pointer tracking feature is enabled (PTEN lead is high). When a 1 is writ-
ten to control bit PARDO, the parity calculation and comparison is for the
data byte only regardless of the state of the PTEN lead. No other action is
taken, other than the alarm indication.
Receive FIFO Error: An alarm occurs when the receive second stage FIFO
in the desynchronizer has either underflowed or overflowed. The FIFO is
recentered automatically. No other action is taken.
Receive RDI Alarm Detected: An alarm occurs when a path RDI alarm has
been detected in bit 5 of the received G1 byte. Control bit RDI10 determines
whether the consecutive event requirement for detection and recovery is 5 or
10.
received C2 byte did not match the microprocessor-written value in location
75H, nor did it match the internal 01H value (when control bit C2FVD is a 0)
for 5 consecutive frames. Recovery occurs when a match occurs in the C2
comparison byte (75H) or internal 01H value (when enabled), for 5 consecu-
tive frames. When control bit C2FVD is a 1, the comparison against the inter-
nal 01H value is disabled. This alarm is disabled if a C2 unequipped alarm
occurs.
C2 Byte Equal to Zero: An alarm occurs when the received C2 byte is all
zeros for 5 consecutive frames, indicating that the VC-4/SPE is carrying an
unequipped channel status (POH bytes and payload bytes are equal to
zero). Recovery occurs when the received C2 byte is not all zeros for 5 con-
secutive frames.
J1 Loss of Lock Alarm: An alarm occurs when the alignment of the J1 trace
identifier label (message) has not been established. The J1 detection circuit
is enabled when control bits J1COM and CCITT are a 1. The J1LOL alarm
will become momentarily active when the following alarms are exited:
DBLOJ1 when PTEN pin is low; E1AIS when EAPE bit is 0; XPAIS or XISTAT
when EAPE bit is 1; RLOP or RPAIS when PTEN pin is high.
J1 Trace Identifier Mismatch: An alarm indicates that the received stable
16-byte message did not match for one message time. Recovery from this
alarm occurs when the J1 state machine losses lock (J1LOL) and then
acquires lock with a 16-byte stable J1 message that matches the J1 compar-
ison message in registers F0H to FFH.
DATA SHEET
- 80 -
Description
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M