txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 5

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

L4M
DATA SHEET
TXC-03456
POH bytes from the Path Overhead interface, or from RAM locations written to by the microprocessor, into the
add bus data stream. The RDI state and FEBE count may be provided from a mate L4M for path-protected ring
configurations.
The Add Block uses drop bus timing signals, add bus timing signals, or external timing signals for outputting
the SDH/STS-3c data signal and parity to the add bus. A feature is also provided that generates the A1, A2, C1
and H1/H2 Transport (SDH Section) Overhead bytes, depending upon the timing mode selected. The C1 byte
value may be a fixed or a microprocessor-written value. The SS-bits in the transmitted pointer may be fixed or
written by the microprocessor. Unused Transport Overhead bytes can be selected to be three-stated or forced
to zero. In the add bus timing mode, the clock and C1J1 signals are monitored for operation. In the external
timing mode, an option is provided which can compensate up to a frame for the position of the C1 byte framing
pulse (EXC1).
The Add Block interface for the add bus timing mode consists of an input clock (ACLK), input C1 and J1 indica-
tor (AC1J1), a separate C1 input (AC1) when enabled, an input SPE indicator (ASPE), output byte data (AD7-
AD0), output parity indication (APAR), and an output add data to bus indicator (ADD). When the L4M is config-
ured to operate in the external timing mode, the add bus signals consist of: external reference input clock
(EXTC) and framing signal (EXC1) (optional), an output clock (ACLK), output C1 and J1 indicator (AC1J1), an
output SPE indicator (ASPE), output byte data (AD7-AD0), output parity indication (APAR), and an output add
data to bus indicator (ADD). When the L4M is configured to operate in the drop bus timing mode, the add bus
signals consist of: an output clock (ACLK), output C1 and J1 indicator (AC1J1), an output SPE indicator
(ASPE), output byte data (AD7-AD0), output parity indication (APAR), and an output add data to bus indicator
(ADD). Odd parity may be calculated over all add bus signals (except the add indicator), or data only.
The Drop Block terminates the drop bus signals. The drop bus signals consists of an input clock (DCLK), input
C1 and J1 indicator (DC1J1), an input SPE indicator (DSPE), input byte data (DD7-DD0), input parity indica-
tion (DPAR), and an optional framing pulse (DC1). When the pointer tracking machine feature is enabled, the
J1 signal in the C1J1 signal must not be present. Odd parity may be checked over all of the drop bus signals,
or for the data byte only. When the pointer tracking machine is enabled, the relative position of C1 can be com-
pensated up to one frame.
The Pointer Tracking Block is enabled by placing a high on the lead designated as PTEN. The pointer tracking
machine meets the pointer tracking requirements specified in ETSI 1015. The Pointer Tracking Block deter-
mines the starting location of the J1 byte in the VC-4 format. The S-bit transition check in the H1 pointer byte
may be disabled in the Pointer Tracking Block. When enabled, the S-bit check can be a fixed value or a value
written by the microprocessor. In addition, the AIS to LOP transition can be disabled to have the Pointer Track-
ing state machine conform to Bellcore standards. The Pointer Tracking Block monitors the pointer bytes for a
path AIS and LOP alarm. Positive, negative and NDF occurrences are counted in 8-bit performance counters.
Having established the starting location of the VC-4, the Decode Block performs Path Overhead byte process-
ing. The POH bytes are written into RAM locations for a microprocessor read cycle in addition to being pro-
vided at a POH interface for external access. Capability is also provided in the L4M for performing the path
trace message comparison for the J1 byte. B3 BIP-8 parity errors and the input FEBE count in the G1 byte are
counted as bit or block errors. The status of the RDI bit is also checked, and an alarm indication provided. The
FEBE count is also provided, along with an RDI indication (as a result of local alarms) to an Alarm Indication
Port for path-protected ring operation. A bit stuffing AIS feature is also provided in addition to using an external
AIS clock to generate line AIS as a result of receive alarms.
The Desynchronizer Block is based on a proprietary TranSwitch design. The Desynchronizer Block removes
the effect on the output signal of systemic jitter due to signal mapping and pointer movements, and consists of
two FIFOs. The FIFOs are monitored for overflow and underflow alarms, and reset automatically when an
alarm is detected. A 15-bit pointer leak register is provided for a microprocessor-written value. The following six
desynchronizer signals are provided: Positive and negative phase detector outputs (CTRL and CTRL), a stuff
indicator (STUFF) that provides the status of the stuff (justification) on a per-subframe basis, positive and neg-
ative justification indicator bits (PJ and NJ), and a pointer leak counter equal to zero indication (PLEQ0). In
TXC-03456-MB
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Ed. 1A, January 2000