txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 75

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

Address
15
16
17
16
7-4
7-0
Bit
3
2
1
0
3
0
C1 Offset
RPSSEL
Transmit
Symbol
TC1DC
FBTOZ
C2FVD
PAISG
UPC1
Receive Pointer S-Bit Select: Enabled when PTEN (pin 2) is high
enabling the pointer tracking machine. This bit works in conjunction with
the RPSDS bit according to the table given above.
Force Unused Bytes To Zero: A 1 forces the unused TOH bytes and
POH bytes (when disabled) to 0. A 0 forces the unused bytes to a high
impedance state.
C2 Fixed Value Disabled: A 1 disables the comparison of the received
C2 byte against the fixed hardware value of 01H in the C2 mismatch
detection circuit. The C2 mismatch comparison is performed against the
microprocessor-written value only.
Microprocessor Writes C1 Value: Enabled when control bit TOHOUT
is a 1 in the drop bus and external timing modes. A 1 enables the micro-
processor to write the value of the transmitted C1 byte. A 0 generates
the value of 01H for the transmitted C1 byte.
Transmit C1 Offset Register: Enabled in the external timing mode only,
when a high is placed on ENABT (pin 36), and when control bit TC1DC
is a 1. The 12-bit register location compensates for the position of the C1
pulse in the EXC1 signal (pin 105). The LSB is bit 0 in 17H, and the
MSB is bit 7 in 16H. The register compensates for up to 2429 (270
columns X 9 rows - 1). For example, if the C1 pulse is in the correct
position, zeros are written to the register. The correct position of the
framing reference is when C1 corresponds to the C11 position in the
SDH/SONET format. When a binary 1 is written to the register (bit 0 in
17H is a 1), it is assumed that the position of the C1 pulse present in the
EXC1 signal is shifted in time one byte and the input pulse corresponds
to the C12 byte position in the SDH/SONET frame. This means that the
starting point for the frame should be one byte earlier. Values written into
the register greater than a binary value of 2429 will be counted as zero
delay.
Transmit C1 Delay Control: Enabled in the external timing mode only,
when a high is placed on ENABT (pin 36). A 1 enables the transmit
12-bit C1 offset register in locations 16H and 17H to compensate for a
C1 offset delay in the transmit direction.
Path AIS Generator Enable: A 1 causes path AIS to be generated in
the transmit direction. The transmitted payload and POH bytes are
forced to the 1 state (if POHDIS=1), in addition to the TOH bytes (when
enabled).
DATA SHEET
- 75 -
Description
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M