DSP56002RC40 Motorola Inc, DSP56002RC40 Datasheet - Page 3
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DSP56002RC40
Manufacturer Part Number
DSP56002RC40
Description
24-BIT DIGITAL SIGNAL PROCESSOR
Manufacturer
Motorola Inc
Datasheet
1.DSP56002RC40.pdf
(110 pages)
- Current page: 3 of 110
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FEATURES
Digital Signal Processing Core
Memory
MOTOROLA
• Efficient 24-bit DSP56000 core
• Up to 40 Million Instructions Per Second (MIPS), 25 ns instruction cycle at
• Up to 240 Million Operations Per Second (MOPS) at 80 MHz; up to 198 MOPS
• Performs a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks
• Highly parallel instruction set with unique DSP addressing modes
• Two 56-bit accumulators including extension bits
• Parallel 24 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
• Double precision 48 48-bit multiply with 96-bit result in 6 instruction cycles
• 56-bit addition/subtraction in 1 instruction cycle
• Fractional and integer arithmetic with support for multiprecision arithmetic
• Hardware support for block-floating point FFT
• Hardware nested DO loops
• Zero-overhead fast interrupts (2 instruction cycles)
• Four 24-bit internal data buses and three 16-bit internal address buses for
• On-chip Harvard architecture permitting simultaneous accesses to program
• 512 24-bit on-chip Program RAM and 64 24-bit bootstrap ROM
• Two 256 24-bit on-chip data RAMs
• Two 256 24-bit on-chip data ROMs containing sine, A-law, and -law tables
• External memory expansion with 16-bit address and 24-bit data buses
• Bootstrap loading from external data bus, Host Interface, or Serial
80 MHz; up to 33 MIPS, 30.3 ns instruction cycle at 66 MHz
at 66 MHz
maximum information transfer on-chip
and two data memories
Communications Interface
DSP56002/D, Rev. 3
DSP56002
Features
iii
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