DSP56002RC40 Motorola Inc, DSP56002RC40 Datasheet - Page 43

• Manufacturer Part Number: DSP56002RC40
• Description: 24-BIT DIGITAL SIGNAL PROCESSOR
• Manufacturer: Motorola Inc

SERIAL COMMUNICATION INTERFACE (SCI) TIMING
C
t
Control Register and T
MOTOROLA
SCC
L
= 50 pF + 2 TTL loads
Num
Num
= Synchronous Clock Cycle Time (For internal clock, t
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Synchronous Clock Cycle—t
Clock Low Period
Clock High Period
< intentionally blank >
Output Data Setup to Clock Falling Edge
(Internal Clock)
Output Data Hold After Clock Rising Edge
(Internal Clock)
Input Data Setup Time Before Clock
Rising Edge (Internal Clock)
Input Data Not Valid Before Clock Rising
Edge (Internal Clock)
Clock Falling Edge to Output Data Valid
(External Clock)
Output Data Hold After Clock Rising Edge
(External Clock)
Input Data Setup Time Before Clock
Rising Edge (External Clock)
Input Data Hold Time After Clock Rising
Edge (External Clock)
Asynchronous Clock Cycle—t
Clock Low Period
Clock High Period
< intentionally blank >
Output Data Setup to Clock Rising Edge (Internal
Clock)
Output Data Hold After Clock Rising Edge
(Internal Clock)
Table 2-9 SCI Synchronous Mode Timing (All Frequencies)
Table 2-10 SCI Asynchronous Mode Timing—1X Clock
C.
Characteristics
) The minimum t
Characteristics
SCC
DSP56002/D, Rev. 3
ACC
SCC
value is 8 T
t
Serial Communication Interface (SCI) Timing
t
t
SCC
SCC
SCC
t
t
SCC
SCC
/4 + T
/4 + T
/4 – T
T
/2 – 10.5
/2 – 10.5
Min
8T
C
SCC
C
—
—
—
16
21
t
t
t
t
.
ACC
ACC
ACC
ACC
+ 3
C
L
L
64T
is determined by the SCI Clock
Min
L
/2 – 11
/2 – 11
—
/2 – 51
/2 – 51
+ 23
– 26
– 8
C
t
SCC
/4 + T
Max
32.5
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
—
—
L
– 5.5
Specifications
Unit
Unit
ns
ns
ns
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
ns
ns
2-17