DSP56002RC40 Motorola Inc, DSP56002RC40 Datasheet - Page 34

• Manufacturer Part Number: DSP56002RC40
• Description: 24-BIT DIGITAL SIGNAL PROCESSOR
• Manufacturer: Motorola Inc

Specifications
Phase Lock Loop (PLL) Characteristics
PHASE LOCK LOOP (PLL) CHARACTERISTICS
RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
C
WS = number of Wait States (0–15) programmed into the external bus access using BCR
1 Wait State = T
2-8
VCO frequency when PLL enabled
PLL external capacitor
(PCAP pin to V
Notes:
Num
L
10
11
12
13
14
15
16
9
= 50 pF + 2 TTL loads
Delay from RESET Assertion to Address High Impedance
(periodically sampled and not 100% tested).
Minimum Stabilization Duration
Delay from Asynchronous RESET Deassertion to First
External Address Output (Internal Reset Deassertion)
Synchronous Reset Setup Time from RESET Deassertion to
first CKOUT transition
Synchronous Reset Delay Time from the first CKOUT
transition to the First External Address Output
Mode Select Setup Time
Mode Select Hold Time
Minimum Edge-Triggered Interrupt Request Assertion
Width
1.
2.
3.
4.
•
•
•
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (All Frequencies)
The E in ET
MF is the PCTL Multiplication Factor bits (MF0–MF11).
The maximum VCO frequency is limited to the internal operation frequency.
Cpcap is the value of the PLL capacitor (connected between PCAP pin and V
The recommended value for Cpcap is: 400 pF for MF 4 and 540 pF for MF > 4.
Characteristics
Internal Oscillator PLL Disabled
External clock PLL Disabled
External clock PLL Enabled
CCP
C
)
4
H
, ET
Table 2-6 Phase Lock Loop (PLL) Characteristics
L
, and ET
Characteristics
1,2,3
C
means external.
DSP56002/D, Rev. 3
2
2
1
MF
Expression
@ MF 4
@ MF > 4
MF
Cpcap
E
f
MF
MF
75000T
2500T
Min
25T
Min
8T
8T
10
8.5
—
21
13
0
C
C
340
380
C
C
C
CCP
MF
MF
) for MF = 1.
Max
9T
8T
f
Max
C
MOTOROLA
T
—
—
—
C
—
—
—
26
480
970
+ 20
C
+ 6
MHz
Unit
pF
pF
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns