DSP56002RC40 Motorola Inc, DSP56002RC40 Datasheet - Page 62

• Manufacturer Part Number: DSP56002RC40
• Description: 24-BIT DIGITAL SIGNAL PROCESSOR
• Manufacturer: Motorola Inc

Specifications
OnCE Port Timing
OnCE PORT TIMING
C
2-36
Num
L
250A
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
= 50 pF + 2 TTL loads
DSCK Low
DSCK High
DSCK Cycle Time
DR Asserted to DSO (ACK) Asserted
DSCK High to DSO Valid
DSCK High to DSO Invalid
DSI Valid to DSCK Low (Setup)
DSCK Low to DSI Invalid (Hold)
Last DSCK Low to OS0–OS1, ACK Active
DSO (ACK) Asserted to First DSCK High
DSO (ACK) Assertion Width
DSO (ACK) Asserted to OS0–OS1 High Impedance
OS0–OS1 Valid to second CKOUT transition
Second CKOUT transition to OS0–OS1 Invalid
Last DSCK Low of Read Register to First DSCK
High of Next Command
Last DSCK Low to DSO Invalid (Hold)
DR Assertion to second CKOUT transition for Wake
Up from Wait state
Second CKOUT transition to DSO after Wake Up
from Wait state
DR Assertion Width
DR Assertion to DSO (ACK) Valid (enter Debug
mode) After Asynchronous Recovery from Wait State
DR Assertion Width to Recover from Stop state
•
•
•
•
•
To recover from Wait state
To recover from Wait state and enter Debug
mode
Stable External Clock, OMR Bit 6 = 0
Stable External Clock, OMR Bit 6 = 1
Stable External Clock, PCTL Bit 17= 1
Characteristics
Table 2-15 OnCE Port Timing
DSP56002/D, Rev. 3
1
2
4T
13T
3T
7T
C
T
17T
17T
Min
C
5T
2T
+ T
C
200
C
40
40
—
15
—
12
15
C
15
15
15
3
3
0
3
– 21
+ T
+ 10
C
C
+ 15
C
C
H
L
– 3
65548T
20T
13T
12T
5T
Max
T
C
C
—
—
—
—
42
—
—
—
—
—
C
—
—
—
—
—
—
—
C
0
C
C
+ T
+ T
+ 7
– 15
MOTOROLA
+ T
L
L
L
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns