DSP56002RC40 Motorola Inc, DSP56002RC40 Datasheet - Page 40
![no-image](/images/no-image-200.jpg)
DSP56002RC40
Manufacturer Part Number
DSP56002RC40
Description
24-BIT DIGITAL SIGNAL PROCESSOR
Manufacturer
Motorola Inc
Datasheet
1.DSP56002RC40.pdf
(110 pages)
- Current page: 40 of 110
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Specifications
Host I/O (HI) Timing
2-14
Notes:
Num
(Output)
(Output)
47
48
49
H0–H7
HREQ
(Input)
(Input)
HACK
HR/W
1.
2.
3.
4.
5.
6.
Delay from HEN Deassertion to HREQ
Assertion for RXL Read
Delay from HEN Deassertion to HREQ
Assertion for TXL Write
Delay from HEN Assertion to HREQ
Deassertion for RXL Read, TXL Write
See
This timing must be adhered to only if two consecutive writes to the TXL are executed without polling
TXDE or HREQ.
This timing must be adhered to only if two consecutive reads from one of these registers are executed
without polling the corresponding status bits or HREQ
HREQ is pulled up by a 1 k resistor.
Specifications are periodically sampled and not 100% tested.
May decrease to 0 ns for future versions.
Table 2-8 Host I/O Timing (Continued)(All Frequencies) (Continued)
Host Port Considerations
Figure 2-12 Host Interrupt Vector Register (IVR) Read
41
35
Characteristics
4,5
4,5
36
DSP56002/D, Rev. 3
31
in
4,5
Section 4
Data Valid
.
42
38
T
37
32
L
T
+ T
L
Min
+ T
3
C
+ T
C
H
Max
—
—
58
MOTOROLA
AA1084
Unit
ns
ns
ns
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