DSP56002RC40 Motorola Inc, DSP56002RC40 Datasheet - Page 47
DSP56002RC40
Manufacturer Part Number
DSP56002RC40
Description
24-BIT DIGITAL SIGNAL PROCESSOR
Manufacturer
Motorola Inc
Datasheet
1.DSP56002RC40.pdf
(110 pages)
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MOTOROLA
Notes:
Num
101A TXC Falling Edge to
102
103
104
105
106
1.
2.
Data Out High
Impedance
FST Input (bl) Setup
Time Before TXC
Falling Edge
FST Input (wl) to
Data Out Enable
from High
Impedance
FST Input (wl)
Setup Time Before
TXC Falling Edge
FST Input Hold
Time After TXC
Falling Edge
Flag Output Valid
After TXC Rising
Edge
Characteristics
For internal clock, External Clock Cycle is defined by I
Periodically sampled and not 100% tested
2
Table 2-11 SSI Timing (Continued)
40 MHZ or 66 MHz
Min
18.3
20.0
18.3
0.8
0.8
3.3
—
—
—
—
DSP56002/D, Rev. 3
T
C
Max
30.8
32.5
20.8
—
—
—
—
—
+ T
H
Synchronous Serial Interface (SSI) Timing
cyc
and SSI control register.
Min
18.3
20.0
18.3
0.8
0.8
3.3
—
—
—
—
80 MHz
T
C
Max
30.8
20.8
—
—
—
—
—
30
+ T
H
Specifications
Case
g ck
x ck
x ck
x ck
x ck
i ck
i ck
i ck
i ck
Unit
2-21
ns
ns
ns
ns
ns
ns
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