ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet - Page 12

• Manufacturer Part Number: ADSP-BF561_06
• Description: Blackfin Embedded Symmetric Multiprocessor
• Manufacturer: AD [Analog Devices]

ADSP-BF561
These modes support ADC/DAC connections, as well as video
communication with hardware signaling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception/transmission of data.
DYNAMIC POWER MANAGEMENT
The ADSP-BF561 provides four power management modes and
one power management state, each with a different perfor-
mance/power profile. In addition, Dynamic Power
Management provides the control functions to dynamically
alter the processor core supply voltage, further reducing power
dissipation. Control of clocking to each of the ADSP-BF561
peripherals also reduces power consumption. See
summary of the power settings for each mode.
Table 3. Power Settings
Full-On Operating Mode—Maximum Performance
In the Full-On mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the default execution state in which maximum performance
can be achieved. The processor cores and all enabled peripherals
run at full speed.
Active Operating Mode—Moderate Power Savings
In the Active mode, the PLL is enabled but bypassed. Because
the PLL is bypassed, the processor’s core clock (CCLK) and sys-
tem clock (SCLK) run at the input clock (CLKIN) frequency. In
this mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the Full-On mode is
entered. DMA access is available to appropriately configured L1
and L2 memories.
In the Active mode, it is possible to disable the PLL through the
PLL Control Register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the Full-On or Sleep modes.
Sleep Operating Mode—High Dynamic Power Savings
The Sleep mode reduces power dissipation by disabling the
clock to the processor core (CCLK). The PLL and system clock
(SCLK), however, continue to operate in this mode. Typically an
external event will wake up the processor. When in the Sleep
mode, assertion of wakeup will cause the processor to sense the
value of the BYPASS bit in the PLL Control register (PLL_CTL).
When in the Sleep mode, system DMA access is only available
to external memory, not to L1 or on-chip L2 memory.
Mode
Full-On
Active
Sleep
Deep Sleep Disabled –
Hibernate
PLL
Enabled
Enabled/
Disabled
Enabled
Disabled –
PLL
Bypassed
No
Yes
–
Core
Clock
(CCLK)
Enabled Enabled On
Enabled Enabled On
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
System
Clock
(SCLK)
Table 3
Rev. A | Page 12 of 60 | May 2006
Core
Power
for a
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The Deep Sleep mode maximizes power savings by disabling the
clocks to the processor cores (CCLK) and to all synchronous
peripherals (SCLK). Asynchronous peripherals will not be able
to access internal resources or external memory. This powered-
down mode can only be exited by assertion of the reset interrupt
(RESET). If BYPASS is disabled, the processor will transition to
the Full-On mode. If BYPASS is enabled, the processor will
transition to the Active mode.
Hibernate Operating State—Maximum Static Power
Savings
The Hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage regu-
lator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (V
Any critical information stored internally (memory contents,
register contents, etc.) must be written to a nonvolatile storage
device prior to removing power if the processor state is to be
preserved. Since V
external pins three-state, unless otherwise specified. This allows
other devices that may be connected to the processor to have
power still applied without drawing unwanted current. The
internal supply regulator can be woken up by asserting the
RESET pin.
Power Savings
As shown in
power domains. The use of multiple power domains maximizes
flexibility, while maintaining compliance with industry stan-
dards and conventions. By isolating the internal logic of the
ADSP-BF561 into its own power domain, separate from the I/O,
the processor can take advantage of Dynamic Power Manage-
ment, without affecting the I/O devices. There are no
sequencing requirements for the various power domains.
Table 4. ADSP-BF561 Power Domains
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The Dynamic Power Management feature of the ADSP-BF561
allows both the processor’s input voltage (V
quency (f
Power Domain
All internal logic
I/O
DDINT
CCLK
) to 0 V to provide the lowest static power dissipation.
) to be dynamically controlled.
Table
DDEXT
4, the ADSP-BF561 supports two different
is still supplied in this mode, all of the
DDINT
) and clock fre-
V
V
V
DDINT
DDEXT
DD
Range