ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet - Page 22

• Manufacturer Part Number: ADSP-BF561_06
• Description: Blackfin Embedded Symmetric Multiprocessor
• Manufacturer: AD [Analog Devices]

ADSP-BF561
TIMING SPECIFICATIONS
Table 11
the ADSP-BF561 clocks. Take care in selecting MSEL, SSEL,
and CSEL ratios so as not to exceed the maximum core clock,
system clock, and Voltage Controlled Oscillator (VCO) operat-
Table 11. Core Clock Requirements—ADSP-BF561SKBCZ500, ADSP-BF561SKB500, ADSP-BF561SKBZ500,
ADSP-BF561SBB500, ADSP-BF561SBBZ500, and ADSP-BF561WBBZ-5A
1
Table 12. Core Clock Requirements—ADSP-BF561SKBCZ600
Table 13. Core Clock Requirements—ADSP-BF561SBB600, ADSP-BF561SBBZ600, ADSP-BF561SKB600 and
ADSP-BF561SKBZ600
1
Table 14. Phase-Locked Loop Operating Conditions
Table 15. Maximum SCLK Conditions
1
Parameter
t
t
t
t
t
Parameter
t
t
t
t
t
Parameter
t
t
t
t
t
t
Parameter
Voltage Controlled Oscillator (VCO) Frequency
Parameter
f
f
Not applicable to ADSP-BF561WBBZ-5A.
External voltage regulator required to ensure proper operation at 600 MHz 1.35 V nominal.
t
SCLK
SCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
SCLK
(= 1/f
SCLK
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
through
) must be greater than or equal to t
1
Table 13
CLKOUT/SCLK Frequency (V
CLKOUT/SCLK Frequency (V
describe the timing requirements for
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
=1.1875 Vminimum)
=1.045 Vminimum)
=0.95 Vminimum)
=0.855 Vminimum)
=0.8 V minimum)
=1.1875 Vminimum)
=1.045 Vminimum)
=0.95 Vminimum)
=0.855 Vminimum)
=0.8 V minimum)
=1.2825 Vminimum)
=1.1875 Vminimum)
=1.045 Vminimum)
=0.95 Vminimum)
=0.855 V minimum)
=0.8 Vminimum)
CCLK
.
1
DDINT
DDINT
1
Rev. A | Page 22 of 60 | May 2006
1
1.14 V)
1.14 V)
ing frequencies, as described in
Page
conditions.
21.
Table 14
describes phase-locked loop operating
Min
50
V
133
100
Min
2.00
2.25
2.86
3.33
4.00
Min
1.66
2.10
2.35
2.66
4.00
Min
1.66
2.00
2.25
2.86
3.33
4.00
DDEXT
= 3.3 V
Absolute Maximum Ratings on
V
133
100
Max
Maximum f
Max
Max
Max
DDEXT
= 2.5 V
CCLK
Unit
MHz
Unit
MHz
MHz
ns
ns
ns
Unit
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns