ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet - Page 14

• Manufacturer Part Number: ADSP-BF561_06
• Description: Blackfin Embedded Symmetric Multiprocessor
• Manufacturer: AD [Analog Devices]

ADSP-BF561
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
Table 5. Example System Clock Ratios
The maximum frequency of the system clock is f
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of f
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table
fast core frequency modifications.
Table 6. Core Clock Ratios
The maximum PLL clock time when a change is programmed
via the PLL_CTL register is 40 µs. The maximum time to change
the internal voltage via the internal voltage regulator is also
40 µs. The reset value for the PLL_LOCKCNT register is 0x200.
This value should be programmed to ensure a 40 µs wakeup
time when either the voltage is changed or a new MSEL value is
programmed. The value should be programmed to ensure an
80 µs wakeup time when both voltage and the MSEL value are
changed. The time base for the PLL_LOCKCNT register is the
period of CLKIN.
Signal Name
SSEL3–0
0001
0110
1010
Signal Name
CSEL1–0
00
01
10
11
Table 5
6. This programmable core clock capability is useful for
illustrates typical system clock ratios.
Divider Ratio
VCO/SCLK
1:1
6:1
10:1
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
SCLK
. The SSEL value can be changed
Example Frequency
Ratios (MHz)
VCO
500
500
200
200
Example Frequency
Ratios (MHz)
VCO
100
300
500
SCLK
CCLK
500
250
50
25
SCLK
100
50
50
. Note that
Rev. A | Page 14 of 60 | May 2006
BOOTING MODES
The ADSP-BF561 has three mechanisms (listed in
automatically loading internal L1 instruction memory or L2
after a reset. A fourth mode is provided to execute from external
memory, bypassing the boot sequence.
Table 7. Booting Modes
The BMODE pins of the Reset Configuration Register, sampled
during power-on resets and software initiated resets, implement
the following modes:
For each of the boot modes, a boot loading protocol is used to
transfer program and data blocks from an external memory
device to their specified memory locations. Multiple memory
blocks may be loaded by any boot sequence. Once all blocks are
loaded, Core A program execution commences from the start of
L1 instruction SRAM (0xFFA0 0000). Core B remains in a held-
off state until Bit 5 of SICA_SYSCR is cleared. After that, Core B
will start execution at address 0xFF60 0000.
In addition, Bit 4 of the Reset Configuration Register can be set
by application code to bypass the normal boot sequence during
a software reset. For this case, the processor jumps directly to
the beginning of L1 instruction memory.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax that was designed for ease of coding
and readability. The instructions have been specifically tuned to
provide a flexible, densely encoded instruction set that compiles
to a very small final memory size. The instruction set also pro-
BMODE1–0
00
01
10
11
• Execute from 16-bit external memory – Execution starts
• Boot from 8-bit/16-bit external flash memory – The
• Boot from SPI serial EEPROM (16-bit addressable) – The
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time,
15-cycle R/W access times, 4-cycle setup).
8-bit/16-bit flash boot routine located in boot ROM mem-
ory space is set up using Asynchronous Memory Bank 0.
All configuration settings are set for the slowest device pos-
sible (3-cycle hold time; 15-cycle R/W access times; 4-cycle
setup).
SPI uses the PF2 output pin to select a single SPI EPROM
device, submits a read command at address 0x0000, and
begins clocking data into the beginning of L1 instruction
memory. A 16-bit addressable SPI-compatible EPROM
must be used.
Description
Execute from 16-bit external memory
(Bypass Boot ROM)
Boot from 8-bit/16-bit flash
Reserved
Boot from SPI serial EEPROM
(16-bit address range)
Table
7) for