ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet - Page 25

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ADSP-BF561_06

Manufacturer Part Number
ADSP-BF561_06
Description
Blackfin Embedded Symmetric Multiprocessor
Manufacturer
AD [Analog Devices]
Datasheet
Asynchronous Memory Write Cycle Timing
Table 18. Asynchronous Memory Write Cycle Timing
1
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
Output pins include AMS3–0, ABE3–0, ADDR25–2, DATA31–0, AOE, AWE.
SARDY
HARDY
DDAT
ENDAT
DO
HO
ADDR25–2
DATA31–0
CLKOUT
ABE3–0
AMSx
ARDY
AWE
ARDY Setup Before CLKOUT
ARDY Hold After CLKOUT
DATA31–0 Disable After CLKOUT
DATA31–0 Enable After CLKOUT
Output Delay After CLKOUT
Output Hold After CLKOUT
2 CYCLES
t
SETUP
END AT
t
DO
t
DO
BE, ADDRESS
WRITE DATA
t
1
1
SARDY
PROGRAMMED WRITE
ACCESS 2 CYCLES
Figure 10. Asynchronous Memory Write Cycle Timing
Rev. A | Page 25 of 60 | May 2006
t
SARDY
EXTENDED
1 CYCLE
ACCESS
t
HO
t
HARDY
1 CYCLE
HOLD
t
HO
Min
4.0
0.0
1.0
0.8
t
DD AT
Max
6.0
6.0
ADSP-BF561
Unit
ns
ns
ns
ns
ns
ns

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