ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet - Page 43

• Manufacturer Part Number: ADSP-BF561_06
• Description: Blackfin Embedded Symmetric Multiprocessor
• Manufacturer: AD [Analog Devices]

TEST CONDITIONS
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section.
shows the measurement point for ac measurements (except out-
put enable/disable). The measurement point V
V
Output Enable Time Measurement
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
The output enable time t
reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure 35 on Page
The time t
nal switches, to when the output voltage reaches V
V
(nominal) = 2.5 V/3.3 V. Time t
output starts driving to when the output reaches the V
or V
Time t
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time t
difference between t
of
The time for the voltage on the bus to decay by V is dependent
on the capacitive load C
can be approximated by the equation:
The time t
The time t
nal switches, to when the output voltage decays V from the
measured output high or output low voltage.
V equal to 0.5 V for V
DDEXT
TRIP
Figure
(low). V
TRIP
(nominal) = 2.5 V/3.3 V.
ENA
(low) trip voltage.
OUTPUT
INPUT
OR
is calculated as shown in the equation:
35.
ENA
DECAY
DIS
_
Measurements (Except Output Enable/Disable)
TRIP
_
MEASURED
MEASURED
Figure 34. Voltage Reference Levels for AC
is calculated with test loads C
(high) is 2.0 V and V
V
t
MEAS
DIS
t
43.
ENA
is the interval from when the reference sig-
is the interval, from when the reference sig-
DIS
=
t
DECAY
_
MEASURED
t
=
DDEXT
L
DIS_MEASURED
ENA
and the load current I
t
ENA_MEASURED
is the interval from the point when a
(nominal) = 2.5 V/3.3 V.
=
and t
TRIP
C
L
DECAY
is the interval from when the
TRIP
–
V
t
(low) is 1.0 V for V
DECAY
as shown on the left side
–
I
t
L
TRIP
L
and I
L
MEAS
. This decay time
is 1.5 V for
TRIP
L
, and with
V
Rev. A | Page 43 of 60 | May 2006
MEAS
Figure 34
(high) or
DIS
TRIP
is the
(high)
DDEXT
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
to be the difference between the ADSP-BF561 processor’s out-
put voltage and the input threshold for the device requiring the
hold time. C
the total leakage or three-state current (per data line). The hold
time will be t
fied in the
for an SDRAM write cycle as shown in
ing on Page
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see
nal) = 2.5 V/3.3 V.
Page 45
delay and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.
(MEASURED)
(MEASURED)
t
DIS
V
V
OUTPUT
Figure 36. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
OH
OL
show how output rise time varies with capacitance. The
PIN
OUTPUT STOPS DRIVING
TO
Timing Specifications on Page 22
26).
L
DECAY
is the total bus capacitance (per data line), and I
DECAY
plus the various output disable times as speci-
Figure 35. Output Enable/Disable
REFERENCE
t
V
using the equation given above. Choose V
V
DIS_MEASURED
Figure 37 on Page 44
OH
OL
SIGNAL
t
Figure
(MEASURED)
(MEASURED) + V
DECAY
HIGH IMPEDANCE STATE
30pF
36). V
t
ENA
V
LOAD
OUTPUT STARTS DRIVING
50
is 1.5 V for V
SDRAM Interface Tim-
through
ADSP-BF561
t
ENA_MEASURED
V
V
(for example t
TRIP
TRIP
t
TRIP
(LOW)
V
(HIGH)
V
OH
OL
Figure 44 on
(MEASURED)
(MEASURED)
V
DDEXT
LOAD
(nomi-
DSDAT
L
is