ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet - Page 40

• Manufacturer Part Number: ADSP-BF561_06
• Description: Blackfin Embedded Symmetric Multiprocessor
• Manufacturer: AD [Analog Devices]

ADSP-BF561
JTAG Test and Emulation Port Timing
Table 30
Table 30. JTAG Port Timing
1
2
3
Parameter
Timing Parameters
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs= DATA31–0, ARDY, TMR2–0, PF47–0, PPIx_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
50 MHz maximum
System Outputs = DATA31–0, ADDR25–2, ABE3–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS3–0, PF47–0, RSCLK0–1, RFS0–1,
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
RESET, NMI0 and NMI1, BMODE1–0, BR, PPIxD7–0.
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPIxD7–0.
and
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse-Width
TDO Delay from TCK Low
System Outputs Delay After TCK Low
Figure 25
TCK
TMS
TDO
SYSTEM
OUTPUTS
INPUTS
TDI
SYSTEM
describe JTAG port operations.
2
(Measured in TCK Cycles)
t
DSYS
t
DTDO
1
t
3
SSYS
1
t
STAP
Rev. A | Page 40 of 60 | May 2006
t
TCK
Figure 25. JTAG Port Timing
t
HSYS
t
HTAP
Min
20
4
4
4
5
4
0
Max
10
12
Unit
ns
ns
ns
ns
ns
TCK
ns
ns