M24LR64-R-DW6T/2 STMICROELECTRONICS [STMicroelectronics], M24LR64-R-DW6T/2 Datasheet - Page 113
M24LR64-R-DW6T/2
Manufacturer Part Number
M24LR64-R-DW6T/2
Description
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.M24LR64-R-DW6T2.pdf
(126 pages)
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M24LR64-R
Table 104. I
1. Values recommended by the I²C-bus Fast-Mode specification.
2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
3. t
4. For a reStart condition, or following a write cycle.
t
t
t
t
t
t
t
t
t
t
t
DXCX
CLDX
CLQX
CLQV
CHDX
DLCL
CHDH
DHDL
W
XH1XH2
Symbol
XL1XL2
t
DL1DL2
t
t
rising edge of SDA.
compatible way with the I
× C
CHCL
CLCH
CLQV
f
C
(2)(3)
(4)
bus
(1)
(1)
is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8V
time constant is less than 500 ns (as specified in
t
t
t
t
t
SU:STO
SU:DAT
HD:DAT
SU:STA
HD:STA
t
t
f
t
HIGH
Alt.
LOW
t
t
BUF
2
SCL
t
DH
t
t
AA
R
C AC characteristics
F
F
Clock frequency
Clock pulse width high
Clock pulse width low
Input signal rise time
Input signal fall time
SDA (out) fall time
Data in set up time
Data in hold time
Data out hold time
Clock low to next data valid (access time)
Start condition set up time
Start condition hold time
Stop condition set up time
Time between Stop condition and next Start condition
I²C write time
2
C specification (which specifies t
Test conditions specified in
Doc ID 15170 Rev 8
Parameter
Figure
SU:DAT
4).
Table 100
(min) = 100 ns), assuming that the R
I
2
C DC and AC parameters
1300
1300
Min.
600
100
100
100
600
600
600
20
20
20
0
CC
in a
Max.
400
300
300
900
100
5
113/126
bus
Unit
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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