M24LR64-R-DW6T/2 STMICROELECTRONICS [STMicroelectronics], M24LR64-R-DW6T/2 Datasheet - Page 47

• Manufacturer Part Number: M24LR64-R-DW6T/2
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24LR64-R
11
11.1
11.1.1
Bit representation and coding
Data bits are encoded using Manchester coding, according to the following schemes. For
the low data rate, same subcarrier frequency or frequencies is/are used, in this case the
number of pulses is multiplied by 4 and all times will increase by this factor. For the Fast
commands using one subcarrier, all pulse numbers and times are divided by 2.
Bit coding using one subcarrier
High data rate
A logic 0 starts with 8 pulses at 423.75 kHz (f
18.88 µs as shown in
Figure 23. Logic 0, high data rate
For the fast commands, a logic 0 starts with 4 pulses at 423.75 kHz (f
unmodulated time of 9.44 µs as shown in
Figure 24. Logic 0, high data rate x2
A logic 1 starts with an unmodulated time of 18.88 µs followed by 8 pulses at 423.75 kHz
(f
Figure 25. Logic 1, high data rate
For the Fast commands, a logic 1 starts with an unmodulated time of 9.44 µs followed by 4
pulses of 423.75 kHz (f
Figure 26. Logic 1, high data rate x2
C
/32) as shown in
Figure
Figure
C
/32) as shown in
25.
23.
Doc ID 15170 Rev 8
37.76µs
37.76µs
Figure
Figure
18.88µs
18.88µs
C
/32) followed by an unmodulated time of
26.
24.
Bit representation and coding
ai12067
ai12066
ai12077
ai12076
C
/32) followed by an
47/126