M24LR64-R-DW6T/2 STMICROELECTRONICS [STMicroelectronics], M24LR64-R-DW6T/2 Datasheet - Page 12

• Manufacturer Part Number: M24LR64-R-DW6T/2
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Description
1
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Description
The M24LR64-R device is a dual-interface, electrically erasable programmable memory
(EEPROM). It features an I
also a contactless memory powered by the received carrier electromagnetic wave.
The M24LR64-R is organized as 8192 × 8 bits in the I
ISO 15693 and ISO 18000-3 mode 1 RF mode.
Figure 1.
I
devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I
bus definition.
The device behaves as a slave in the I
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in
When writing data to the memory, the device inserts an acknowledge bit during the 9
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
In the ISO15693/ISO18000-3 mode 1 RF mode, the M24LR64-R is accessed via the
13.56 MHz carrier electromagnetic wave on which incoming data are demodulated from the
received signal amplitude modulation (ASK: amplitude shift keying). The received ASK wave
is 10% or 100% modulated with a data rate of 1.6 Kbit/s using the 1/256 pulse coding mode
or a data rate of 26 Kbit/s using the 1/4 pulse coding mode.
Outgoing data are generated by the M24LR64-R load variation using Manchester coding
with one or two subcarrier frequencies at 423 kHz and 484 kHz. Data are transferred from
the M24LR64-R at 6.6 Kbit/s in low data rate mode and 26 Kbit/s high data rate mode. The
M24LR64-R supports the 53 Kbit/s in high data rate mode in one subcarrier frequency at
423 kHz.
The M24LR64-R follows the ISO 15693 and ISO 18000-3 mode 1 recommendation for
radio-frequency power and signal interface.
2
C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The
Logic diagram
Table
2
E0-E1
C interface and can be operated from a V
SCL
Doc ID 15170 Rev 8
2), terminated by an acknowledge bit.
2
2
C protocol, with all memory operations synchronized
V CC
M24LR64-R
V SS
2
C mode and as 2048 × 32 bits in the
SDA
AC0
AC1
CC
power supply. It is
M24LR64-R
AI15106b
th
2
bit
C