M24LR64-R-DW6T/2 STMICROELECTRONICS [STMicroelectronics], M24LR64-R-DW6T/2 Datasheet - Page 33

• Manufacturer Part Number: M24LR64-R-DW6T/2
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24LR64-R
5.9
Minimizing system delays by polling on ACK
During the internal write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum I²C write time (t
shown in
can be used by the bus master.
The sequence, as shown in
1.
2.
3.
Initial condition: a write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Table 104
, but the typical time is shorter. To make use of this, a polling sequence
Figure
Doc ID 15170 Rev 8
12, is:
I
2
C device operation
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