SAF-C161S-L25M Infineon Technologies AG, SAF-C161S-L25M Datasheet - Page 11

• Manufacturer Part Number: SAF-C161S-L25M
• Description: 16-Bit Single-Chip Microcontroller
• Manufacturer: Infineon Technologies AG

Table 2
Symbol Pin
PORT1
P1L.0-7
P1H.0-7
RSTIN
RST
OUT
NMI
Data Sheet
No.
47-54
55-62
65
66
67
Pin Definitions and Functions (cont’d)
Input
Outp.
IO
I/O
O
I
Function
PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the
16-bit address bus (A) in demultiplexed bus modes and also
after switching from a demultiplexed bus mode to a
multiplexed bus mode.
Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the C161S. An
internal pull-up resistor permits power-on reset using only a
capacitor connected to
A spike filter suppresses input pulses < 10 ns. Input pulses
> 100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN line is internally pulled low
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table.
Note: To let the reset configuration of PORT0 settle and to
Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C161S to go into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
let the PLL lock a reset duration of approx. 1 ms is
recommended.
7
V
SS
.
General Device Information
V1.0, 2003-11
C161S