SAF-C161S-L25M Infineon Technologies AG, SAF-C161S-L25M Datasheet - Page 69

• Manufacturer Part Number: SAF-C161S-L25M
• Description: 16-Bit Single-Chip Microcontroller
• Manufacturer: Infineon Technologies AG

Table 19
ALE cycle time = 4 TCL + 2
Parameter
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
1) RW-delay and
2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
Data Sheet
Therefore address changes before the end of RD have no impact on read cycles.
specified together with the address and signal BHE (see figures below).
Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
t
1)
A
refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
Symbol
t
t
t
68
55
57
t
A
+
t
C
SR –
CC -16 +
CC 9 +
+
t
F
Min.
Max. CPU Clock
(100 ns at 20 MHz CPU clock without waitstates)
t
= 20 MHz
F
65
t
F
Max.
5 +
–
–
t
F
1 / 2TCL = 1 to 20 MHz
Min.
–
-16 +
TCL - 16
+
Variable CPU Clock
t
F
Timing Characteristics
t
F
Max.
TCL - 20
+ 2
–
–
t
A
V1.0, 2003-11
+
t
F
1)
C161S
Unit
ns
ns
ns