SAF-C161S-L25M Infineon Technologies AG, SAF-C161S-L25M Datasheet - Page 49

• Manufacturer Part Number: SAF-C161S-L25M
• Description: 16-Bit Single-Chip Microcontroller
• Manufacturer: Infineon Technologies AG

levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the
logic levels on pins P0.15-13 (P0H.7-5).
Table 13
generation mode.
Table 13
CLKCFG
(P0H.7-5)
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
1) The external clock input range refers to a CPU clock range of 10 … 25 MHz (PLL operation). If the on-chip
2) The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation
When prescaler operation is configured (CLKCFG = 001
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of
the duration of an individual TCL) is defined by the period of the input clock
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.
=
to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency
does not change abruptly.
Due to this adaptation to the input clock the frequency of
it is locked to
duration of individual TCLs.
Data Sheet
f
OSC
oscillator is used together with a crystal, the oscillator frequency is limited to a range of 4 MHz to 16 MHz.
F). With every F’th transition of
associates the combinations of these three bits with the respective clock
CPU Frequency
f
f
f
f
f
f
f
f
f
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
CPU
C161S Clock Generation Modes
f
OSC
=
/ 2
f
CPU
. The slight variation causes a jitter of
4
3
2
5
1
1.5
2.5
f
OSC
is half the frequency of
F
f
OSC
External Clock
Input Range
2.5 to 6.25 MHz
3.33 to 8.33 MHz
5 to 12.5 MHz
2 to 5 MHz
1 to 25 MHz
6.66 to 16.67 MHz
2 to 50 MHz
4 to 10 MHz
for any TCL.
f
OSC
45
the PLL circuit synchronizes the CPU clock
1)
f
Table
OSC
and the high and low time of
13). The PLL multiplies the input
Notes
Default configuration
–
–
–
Direct drive
–
CPU clock via prescaler
–
B
) the CPU clock is derived from
f
CPU
f
CPU
is constantly adjusted so
Timing Characteristics
2)
which also effects the
V1.0, 2003-11
f
OSC
f
C161S
CPU
.
f
(i.e.
CPU