SAF-C161S-L25M Infineon Technologies AG, SAF-C161S-L25M Datasheet - Page 48

• Manufacturer Part Number: SAF-C161S-L25M
• Description: 16-Bit Single-Chip Microcontroller
• Manufacturer: Infineon Technologies AG

5
5.1
The internal operation of the C161S is controlled by the internal CPU clock
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see
Figure 10
The CPU clock signal
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
be regarded when calculating the timings for the C161S.
Note: The example for PLL operation shown in
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic
Data Sheet
Phase Locked Loop Operation
f
f
Direct Clock Drive
f
f
Prescaler Operation
f
f
OSC
CPU
OSC
CPU
OSC
CPU
Timing Characteristics
Definition of Internal Timing
Generation Mechanisms for the CPU Clock
f
CPU
can be generated from the oscillator clock signal
44
Figure 10
refers to a PLL factor of 4.
TCL
f
Timing Characteristics
CPU
TCL
. This influence must
TCL
TCL
TCL
TCL
MCT04338
Figure
V1.0, 2003-11
f
CPU
f
C161S
OSC
. Both
10).
via