SAF-C161S-L25M Infineon Technologies AG, SAF-C161S-L25M Datasheet - Page 9

• Manufacturer Part Number: SAF-C161S-L25M
• Description: 16-Bit Single-Chip Microcontroller
• Manufacturer: Infineon Technologies AG

Table 2
Symbol Pin
XTAL1
XTAL2
P3
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
Data Sheet
No.
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
23
24
Pin Definitions and Functions
Input
Outp.
I
O
IO
I
O
I
I
I
I
I/O
I/O
O
I/O
O
O
I/O
IO
O
O
O
O
O
O
Function
XTAL1:
XTAL2:
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics (see
Port 3 is a 12-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 3 outputs can be configured as
push/pull or open drain drivers.
The following Port 3 pins also serve for alternate functions:
CAPIN
T3OUT
T3EUD
T4IN
T3IN
T2IN
MRST
MTSR
TxD0
RxD0
BHE
WRH
SCLK
Port 4 is a 6-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
Port 4 can be used to output the segment address lines:
A16
A17
A18
A19
A20
A21
Input to the oscillator amplifier and input to the
internal clock generator
Output of the oscillator amplifier circuit.
GPT2 Register CAPREL Capture Input
GPT1 Timer T3 Toggle Latch Output
GPT1 Timer T3 External Up/Down Control Input
GPT1 Timer T4 Count/Gate/Reload/Capture Inp.
GPT1 Timer T3 Count/Gate Input
GPT1 Timer T2 Count/Gate/Reload/Capture Inp.
SSC Master-Receive/Slave-Transmit Inp./Outp.
SSC Master-Transmit/Slave-Receive Outp./Inp.
ASC0 Clock/Data Output (Async./Sync.)
External Memory High Byte Enable Signal,
External Memory High Byte Write Strobe
SSC Master Clock Output / Slave Clock Input.
Least Significant Segment Address Line
Segment Address Line
Segment Address Line
Segment Address Line
Segment Address Line
Segment Address Line
ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
5
Chapter
5.4) must be observed.
General Device Information
V1.0, 2003-11
C161S