SAF-C161S-L25M Infineon Technologies AG, SAF-C161S-L25M Datasheet - Page 56

• Manufacturer Part Number: SAF-C161S-L25M
• Description: 16-Bit Single-Chip Microcontroller
• Manufacturer: Infineon Technologies AG

Table 16
ALE cycle time = 6 TCL + 2
Parameter
ALE fall. edge to RdCS,
WrCS (with RW delay)
ALE fall. edge to RdCS,
WrCS (no RW delay)
Address float after
RdCS, WrCS (with RW
delay)
Address float after
RdCS, WrCS (no RW
delay)
RdCS to Valid Data In
(with RW delay)
RdCS to Valid Data In
(no RW delay)
RdCS, WrCS Low Time
(with RW delay)
RdCS, WrCS Low Time
(no RW delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
Address hold after
RdCS, WrCS
Data hold after WrCS
1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
Data Sheet
specified together with the address and signal BHE (see figures below).
Multiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
42
43
44
45
46
47
48
49
50
51
52
54
56
t
A
+
t
C
CC 16 +
CC -4 +
CC –
CC –
SR –
SR –
CC 30 +
CC 50 +
CC 26 +
SR 0
SR –
CC 20 +
CC 20 +
+
t
F
Min.
Max. CPU Clock
(120 ns at 25 MHz CPU clock without waitstates)
= 25 MHz
52
t
t
t
t
t
t
t
A
A
C
C
C
F
F
Max.
–
–
0
20
16 +
36 +
–
–
–
–
20 +
–
–
t
t
t
C
C
F
1 / 2TCL = 1 to 25 MHz
Min.
TCL - 4
+
-4
+
–
–
–
–
2TCL - 10
+
3TCL - 10
+
2TCL - 14
+
0
–
2TCL - 20
+
2TCL - 20
+
Variable CPU Clock
t
t
t
t
t
t
t
A
A
C
C
C
F
F
Timing Characteristics
Max.
–
–
0
TCL
2TCL - 24
+
3TCL - 24
+
–
–
–
–
2TCL - 20
+
–
–
t
t
t
C
C
F
V1.0, 2003-11
C161S
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns