MCIMX285AJM4A Freescale Semiconductor, MCIMX285AJM4A Datasheet - Page 35

• Manufacturer Part Number: MCIMX285AJM4A
• Description: Processors - Application Specialized CATSKILLS REV 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX285AJM4A

• Product Category: Processors - Application Specialized
• Core: ARM926EJ-S
• Processor Series: i.MX28
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Operating Supply Voltage: 1.35 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Memory Type: L1 Cache, ROM, SRAM

3.5.4.1.4
The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3
MII specification. However the ENET can function correctly with a maximum MDC frequency of
15 MHz.
Figure 12
shown in the figure.
3.5.4.2
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference
clock. ENET0_RX_DV is used as the CRS_DV in RMII. Other signals under RMII mode include
ENET0_TX_EN, ENET0_TXD[1:0], ENET0_RXD[1:0] and ENET0_RX_ER.
Freescale Semiconductor
M10
M11
M12
M13
M14
M15
ID
ENET0_MDIO (output)
ENET0_MDC (output)
ENET0_MDIO (input)
ENET0_MDC falling edge to ENET0_MDIO output invalid (min.
propagation delay)
ENET0_MDC falling edge to ENET0_MDIO output valid (max.
propagation delay)
ENET0_MDIO (input) to ENET0_MDC rising edge setup
ENET0_MDIO (input) to ENET0_MDC rising edge hold
ENET0_MDC pulse width high
ENET0_MDC pulse width low
shows MII asynchronous input timings.
RMII Mode Timing
MII Serial Management Channel Timing (ENET0_MDIO and ENET0_MDC)
Figure 12. MII Serial Management Channel Timing Diagram
i.MX28 Applications Processors for Automotive Products, Rev. 3
Table 41. MII Serial Management Channel Timing
Characteristic
M12
M13
Table 41
M14
describes the timing parameters (M10–M15)
Min.
40%
40%
M10
18
—
0
0
M11
M15
Max.
60%
60%
—
—
—
5
Electrical Characteristics
ENET0_MDC period
ENET0_MDC period
Unit
ns
ns
ns
ns
35