MCIMX285AJM4A Freescale Semiconductor, MCIMX285AJM4A Datasheet - Page 7

• Manufacturer Part Number: MCIMX285AJM4A
• Description: Processors - Application Specialized CATSKILLS REV 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX285AJM4A

• Product Category: Processors - Application Specialized
• Core: ARM926EJ-S
• Processor Series: i.MX28
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Operating Supply Voltage: 1.35 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Memory Type: L1 Cache, ROM, SRAM

Freescale Semiconductor
FlexCAN(2)
Mnemonic
L2 Switch
DIGCTL
HSADC
DUART
DFLPT
ICOLL
Block
ENET
I
GPMI
2
EMI
C(2)
Default
first-level page
table
and on-chip
RAM
memory
interface
Controller
area network
module
General-pur-
pose media
interface
ADC
I
3-Port L2
Switch
Digital control
Debug UART Connectivity
External
Ethernet MAC
Controller
High-speed
Interrupt
Collector
2
Block Name
C module
i.MX28 Applications Processors for Automotive Products, Rev. 3
Table 4. i.MX28 Digital and Analog Modules (continued)
System control The DFLPT provides a unique method of implementing the ARM MMU
System control The digital control module includes sections for controlling the SRAM, the
peripherals
Connectivity
peripherals
Connectivity
peripherals
Connectivity
peripherals
Connectivity
peripherals
Connectivity
peripherals
Connectivity
peripherals
System control The ARM9 CPU core has two interrupt input lines, IRQ and FIQ. The interrupt
Network Control Programmable 3-Port Ethernet Switch with QOS
Subsystem
first-level page table (L1PT) using a hardware-based approach.
performance monitors, high-entropy pseudo-random number seed,
free-running microseconds counter, and other chip control functions.
The Debug UART performs the following data conversions:
The i.MX28 supports off-chip DRAM storage through the EMI controller,
which is connected to the four internal AHB/AXI busses. The EMI supports
multiple external memory types, including:
Ethernet MAC controller connected to the uDMA (unified DMA). Supports
10/100 Mbps with TCP/UDP/IP Acceleration and IEEE 1588 Functions; also
supports RMII or MII connectivity.
The Controller Area Network (CAN) protocol is a message based protocol
used for serial data. It was designed specifically for automotive but is also
used in industrial control and medical applications. The serial data bus runs
at 1 Mbps.
The General-Purpose Media Interface (GPMI) controller is a flexible NAND
Flash controller with 8-bit data width, up to 50-MBps I/O speed and individual
chip select and DMA channels for up to 8 NAND devices. It also provides a
interface to 20-bit BCH for ECC.
The high-speed ADC block is designed to sample an analog input with 12-bit
resolution and a sample rate of up to 2 Msps. The output of the HSADC block
can be moved to the external memory through APBH-DMA. A typical user
case of the HSADC is to work with the PWM block to drive an external linear
image scanner sensor.
The I
peripherals or host controllers. The I
master or I
also controlled by CPU in PIO or PIO queue modes. It supports both 7-bit and
10-bit device address in master mode, and has programmable 7-bit address
in slave mode.
collector (ICOLL) can steer any of 128 interrupt sources to either the FIQ or
IRQ line of the ARM9 CPU.
• Serial-to-parallel conversion on data received from a peripheral device
• Parallel-to-serial conversion on data transmitted to the peripheral device
• 1.8-V Mobile DDR1 (LP-DDR1)
• Standard 1.8-V DDR2
• Low Voltage 1.5-V DDR2 (LV-DDR2)
2
C is a standard two-wire serial interface used to connect the chip with
2
C slave mode. Each I
Brief Description
2
C has a dedicated DMA channel and can
2
C operates up to 400 kbps in either I
Features
2
C
7