MCIMX285AJM4A Freescale Semiconductor, MCIMX285AJM4A Datasheet - Page 36

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MCIMX285AJM4A

Manufacturer Part Number
MCIMX285AJM4A
Description
Processors - Application Specialized CATSKILLS REV 1.1
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet

Specifications of MCIMX285AJM4A

Product Category
Processors - Application Specialized
Core
ARM926EJ-S
Processor Series
i.MX28
Data Bus Width
32 bit
Data Ram Size
128 KB
Operating Supply Voltage
1.35 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Memory Type
L1 Cache, ROM, SRAM
Electrical Characteristics
Figure 13
figure.
3.5.5
The following timing specifications are given as a guide for a TPA that supports TRACECLK
(ETM_TCLK) frequencies up to 80 MHz. TRACECLK is the ETM_TCLK signal which can be made
functional by using some IOMUX configurations. See the reference manual for detailed information.
3.5.5.1
This section describes TRACECLK timings.
36
M16
M17
M18
M19
M20
M21
ENET0_TXD[1:0] (output)
ENET0_TX_EN
ENET0_RXD[1:0]
ID
ENET0_RX_ER
ENET_CLK (input)
ENET_CLK pulse width high
ENET_CLK pulse width low
ENET_CLK to ENET0_TXD[1:0], ENET0_TX_EN invalid
ENET_CLK to ENET0_TXD[1:0], ENET0_TX_EN valid
ENET0_RXD[1:0], CRS_DV(ENET0_RX_DV), ENET0_RX_ER to
ENET_CLK setup
ENET_CLK to ENET0_RXD[1:0], ENET0_RX_DV, ENET0_RX_ER hold
shows RMII mode timings.
CRS_DV (input)
Coresight ETM9 AC Interface Timing
TRACECLK Timing
i.MX28 Applications Processors for Automotive Products, Rev. 3
Figure 13. RMII Mode Signal Timing Diagram
Characteristic
Table 42
Table 42. RMII Signal Timing
M20
M18
describes the timing parameters (M16–M21) shown in the
M21
M19
M16
M17
Min.
35%
35%
3
2
2
Max.
65%
65%
12
Freescale Semiconductor
ENET_CLK period
ENET_CLK period
Unit
ns
ns
ns
ns

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