MCIMX285AJM4A Freescale Semiconductor, MCIMX285AJM4A Datasheet - Page 44

• Manufacturer Part Number: MCIMX285AJM4A
• Description: Processors - Application Specialized CATSKILLS REV 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX285AJM4A

• Product Category: Processors - Application Specialized
• Core: ARM926EJ-S
• Processor Series: i.MX28
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Operating Supply Voltage: 1.35 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Memory Type: L1 Cache, ROM, SRAM

Electrical Characteristics
3.5.9
The I
The following section describes I
Figure 25
(IC1–IC11) shown in the figure.
1
2
3
4
44
I2C_SDA
I2C_SCL
A device must internally provide a hold time of at least 300 ns for the I2C_SDA signal in order to bridge the undefined region
of the falling edge of I2C_SCL.
The maximum IC4 has to be met only if the device does not stretch the LOW period (ID no IC5) of the I2C_SCL signal.
A fast-mode I2C bus device can be used in a standard-mode I
of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2C_SCL signal.
If such a device does stretch the LOW period of the I2C_SCL signal, it must output the next data bit to the I2C_SDA line
max_rise_time (ID No IC9) + data_setup_time (ID No IC7) = 1000 + 250 = 1250 ns (according to the standard-mode I
specification) before the I2C_SCL line is released.
C
IC10
IC11
IC12
b
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
ID
= total capacitance of one bus line in pF.
2
C module is designed to support up to 400-Kbps I
shows the timing of the I
I2C_SCL cycle time
Hold time (repeated) START condition
Set-up time for STOP condition
Data hold time
HIGH Period of I2C_SCL clock
LOW Period of the I2C_SCL clock
Set-up time for a repeated START condition
Data set-up time
Bus free time between a STOP and START condition
Rise time of both I2C_SDA and I2C_SCL signals
Fall time of both I2C_SDA and I2C_SCL signals
Capacitive load for each bus line (C
Inter IC (I
IC2
START
2
i.MX28 Applications Processors for Automotive Products, Rev. 3
IC10
C) Timing
IC6
Table 49. I
IC8
IC1
Parameter
IC10
2
Figure 25. I
C SDA and SCL signal timings.
2
IC5
2
C module.
C Module Timing Parameters: 1.8 V
IC4
b
)
2
C Module Timing Diagram
IC11
Table 49
IC11
2
C bus system, but the requirement of Set-up time (ID No IC7)
2
describes the I
C connection compliant with I
IC7
START
Standard Mode
Min.
250
4.0
4.0
4.0
4.7
4.7
4.7
10
0
—
—
—
1
2
C module timing parameters
–
3.45
Max.
1000
300
400
3.6 V
—
—
—
—
—
—
—
—
2
IC3
20+0.1C
20+0.1C
STOP
Min.
100
2.5
0.6
0.6
0.6
1.3
0.6
1.3
0
—
Fast Mode
Freescale Semiconductor
1
3
b
b
2
4
4
C bus protocol.
IC9
Max.
0.9
300
300
400
—
—
—
—
—
—
—
—
START
2
2
Unit
C bus
μs
μs
μs
μs
μs
μs
μs
ns
μs
ns
ns
pF