XE8000EV120 Semtech, XE8000EV120 Datasheet - Page 56

• Manufacturer Part Number: XE8000EV120
• Description: BOARD EVAL FOR SX8722I070TRLF
• Manufacturer: Semtech
• Series: ZoomingADC™r

Specifications of XE8000EV120

• Number Of Adc's: 1
• Number Of Bits: 16
• Data Interface: I²C
• Inputs Per Adc: 7 Single or 4 Differential
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Utilized Ic / Part: SX8722
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: XM8000EV120; XM8000EV120

12.5. ZoomingADC™ registers table
In table below the configuration of the peripheral registers is detailed. The system has a bank of eight 8-bit registers: six
registers are used to configure the acquisition chain (CxZAdcReg1 to 6), and two registers are used to store the output code
of the analog-to-digital conversion (CxDataOutMSB & LSB).
Note Bits labelled R are reserved
With:
OUT:
SET_NELC:
SET_OSR:
CONT:
IB_AMP_ADC:
IB_AMP_PGA:
ENABLE:
FIN:
PGA1_GAIN:
PGA2_GAIN:
ACS - Revision 4.2
©2008 Semtech Corp.
CxDataOutLSB
CxDataOutMSB
CxZadcReg1
Default values
CxZadcReg2
Default value
CxZadcReg3
Default value
CxZadcReg4
Default value
CxZadcReg5
Default value
CxZadcReg6
Default value
Register Name
ADVANCED COMMUNICATIONS & SENSING
PGA1_GAIN
100% of nominal current). To be used for low-power, low-speed operation.
(r) digital output code of the analog-to-digital converter. (MSB = OUT[15])
(rw) sets the number of elementary conversions to 2
chopped between elementary conversions (1,2,4,8).
(rw) sets the over-sampling rate (OSR) of an elementary conversion to 2
1024.
(rw) setting this bit starts a conversion. A new conversion will automatically begin as long as the bit remains at 1.
(rw) sets the bias current in the ADC to 0.25 x (1+ IB_AMP_ADC[1:0]) of the normal operation current (25, 50, 75 or
(rw) sets the bias current in the PGAs to 0.25 x (1+ IB_AMP_PGA[1:0]) of the normal operation current (25, 50, 75 or
100% of nominal current). To be used for low-power, low-speed operation.
are disabled are bypassed.
(rw) These bits set the sampling frequency of the acquisition chain. Expressed as a fraction of the oscillator frequency,
the sampling frequency is given as: 00 ' 1/4 f
(rw) sets the gain of the first stage: 0 ' 1, 1 ' 10.
(rw) sets the gain of the second stage: 00 ' 1, 01 ' 2, 10 ' 5, 11 ' 10.
(rw) enables the ADC modulator (bit 0) and the different stages of the PGAs (PGAi by bit i = 1,2,3). PGA stages that
IB_AMP_ADC[1:0]
R
R
7
0
0
0
0
FIN[1:0]
00
11
October 2008
R
6
0
SET_NC[1:0]
01
Table 40. ZoomingADC registers
IB_AMP_PGA[1:0]
PGA2_GAIN[1:0]
5
00
11
Page 56
RC
, 01 ' 1/8 f
4
Bit position
SET_NELC[1:0]
OUT[15:8]
OUT[7:0]
PGA3_OFFSET[6:0]
High gain acquisition for sensor interface
PGA3_GAIN[6:0]
RC
SET_OSR[2:0]
, 10 ' 1/32 f
AMUX[4:0]
0000000
0000000
00000
010
3
. To compensate for offsets, the input signal is
RC
(3+SET_OSR[2:0])
, 11' ~8kHz.
2
PGA2_OFFSET
ENABLE[3:0]
0001
0000
. OSR = 8, 16, 32, ..., 512,
R
1
0
DATASHEET
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SX8722
VMUX
R
0
0
0