ATTINY20-EK1 Atmel, ATTINY20-EK1 Datasheet - Page 152

• Manufacturer Part Number: ATTINY20-EK1
• Description: KIT EVAL TOUCH ATTINY20
• Manufacturer: Atmel

Specifications of ATTINY20-EK1

• Sensor Type: *
• Sensing Range: *
• Interface: *
• Sensitivity: *
• Voltage - Supply: *
• Embedded: *
• Utilized Ic / Part: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: TinyAVR
• Kit Contents: Board
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: ATtiny20
• Tool / Board Applications: Microcontroller
• Rohs Compliant: Yes
• Tool Type: Development Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor To Be Evaluated: ATtiny20
• Interface Type: Touch
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18. Programming Interface
18.1
18.2
18.3
152
Features
Overview
Physical Layer of Tiny Programming Interface
ATtiny20
•
•
The Tiny Programming Interface (TPI) supports external programming of all Non-Volatile Memo-
ries (NVM). Memory programming is done via the NVM Controller, by executing NVM controller
commands as described in
The Tiny Programming Interface (TPI) provides access to the programming facilities. The inter-
face consists of two layers: the access layer and the physical layer. The layers are illustrated in
Figure
Figure 18-1. The Tiny Programming Interface and Related Internal Interfaces
Programming is done via the physical interface. This is a 3-pin interface, which uses the RESET
pin as enable, the TPICLK pin as the clock input, and the TPIDATA pin as data input and output.
NVM can be programmed at 5V, only.
The TPI physical layer handles the basic low-level serial communication. The TPI physical layer
uses a bi-directional, half-duplex serial receiver and transmitter. The physical layer includes
serial-to-parallel and parallel-to-serial data conversion, start-of-frame detection, frame error
detection, parity error detection, parity generation and collision detection.
Physical Layer:
Access Layer:
– Synchronous Data Transfer
– Bi-directional, Half-duplex Receiver And Transmitter
– Fixed Frame Format With One Start Bit, 8 Data Bits, One Parity Bit And 2 Stop Bits
– Parity Error Detection, Frame Error Detection And Break Character Detection
– Parity Generation And Collision Detection
– Automatic Guard Time Insertion Between Data Reception And Transmission
– Communication Based On Messages
– Automatic Exception Handling Mechanism
– Compact Instruction Set
– NVM Programming Access Control
– Tiny Programming Interface Control And Status Space Access Control
– Data Space Access Control
18-1.
TPIDATA
TPICLK
RESET
TINY PROGRAMMING INTERFACE (TPI)
PHYSICAL
LAYER
“Memory Programming” on page
ACCESS
LAYER
163.
DATA BUS
NON-VOLATILE
CONTROLLER
MEMORIES
NVM
8235B–AVR–04/11