PIC16F630-I/SL Microchip Technology, PIC16F630-I/SL Datasheet
PIC16F630-I/SL
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PIC16F630-I/SL Summary of contents
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... Microchip Technology Inc. PIC16F630/676 Data Sheet 14-Pin, Flash-Based 8-Bit CMOS Microcontrollers DS40039F ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Memory Device Flash (words) PIC16F630 1024 PIC16F676 1024 2010 Microchip Technology Inc. PIC16F630/676 Low-Power Features: • Standby Current 2.0V, typical • Operating Current: - 8.5 kHz, 2.0V, typical - 100 MHz, 2.0V, typical • Watchdog Timer Current - 300 nA @ 2.0V, typical • ...
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... PIC16F630/676 Pin Diagrams 14-pin PDIP, SOIC, TSSOP RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/V RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/AN3/CLKOUT RA3/MCLR/V DS40039F-page RA0/CIN+/ICSPDAT 3 12 RA1/CIN-/ICSPCLK 4 11 RA2/COUT/T0CKI/INT PP RC5 5 RC0 10 RC4 6 RC1 9 RC3 7 RC2 RA0/AN0/CIN+/ICSPDAT 3 12 RA1/AN1/CIN-/ RA2/AN2/COUT/T0CKI/INT RC5 5 10 RC0/AN4 RC4 6 RC1/AN5 9 RC3/AN7 7 RC2/AN6 8 /ICSPCLK REF ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2010 Microchip Technology Inc. PIC16F630/676 DS40039F-page 5 ...
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... PIC16F630/676 NOTES: DS40039F-page 6 2010 Microchip Technology Inc. ...
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... The PIC16F630 and PIC16F676 devices are covered by this Data Sheet. They are identical, except the PIC16F676 has a 10-bit A/D converter. They come in 14-pin PDIP, SOIC and TSSOP packages. Figure 1-1 shows a block diagram of the PIC16F630/676 devices. Table 1-1 shows the pinout description. INT 13 ...
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... PIC16F630/676 TABLE 1-1: PIC16F630/676 PINOUT DESCRIPTION Name Function RA0/AN0/CIN+/ICSPDAT RA0 AN0 CIN+ ICSPDAT RA1/AN1/CIN-/V / RA1 REF ICSPCLK AN1 CIN- V REF ICSPCLK RA2/AN2/COUT/T0CKI/INT RA2 AN2 COUT T0CKI INT RA3/MCLR/V RA3 PP MCLR V PP RA4/T1G/AN3/OSC2/ RA4 CLKOUT T1G AN3 OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN RA5 ...
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... MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC16F630/676 devices have a 13-bit program counter capable of addressing program memory space. Only the first (0000h-03FFh) for the PIC16F630/676 devices is physically imple- mented. Accessing a location above these boundaries will cause a wrap around within the first space. ...
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... The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. DS40039F-page 10 FIGURE 2-2: DATA MEMORY MAP OF THE PIC16F630/676 File Address (1) Indirect addr. 00h Indirect addr. TMR0 ...
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... TABLE 2-1: PIC16F630/676 SPECIAL REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module’s Register 02h PCL Program Counter’s (PC) Least Significant Byte 03h ...
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... PIC16F630/676 TABLE 2-2: PIC16F630/676 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RAPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte 83h ...
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... Status bits. For other instructions not affect- ing any Status bits, see Section 10.0 “Instruction Set Summary”. Note 1: Bits IRP and RP1 (STATUS<7:6>) are not used by the PIC16F630/676 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products. ...
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... PIC16F630/676 2.2.2.2 OPTION Register The OPTION register is a readable and writable register, which contains various control bits to configure: • TMR0/WDT prescaler • External RA2/INT interrupt • TMR0 • Weak pull-ups on PORTA REGISTER 2-2: OPTION_REG — OPTION REGISTER (ADDRESS: 81h) R/W-1 R/W-1 ...
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... T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit. Legend Readable bit - n = Value at POR 2010 Microchip Technology Inc. PIC16F630/676 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User ...
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... PIC16F630/676 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: PIE1 — PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) R/W-0 R/W-0 EEIE ADIE bit 7 bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt ...
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... TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Legend Readable bit - n = Value at POR 2010 Microchip Technology Inc. PIC16F630/676 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User ...
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... PIC16F630/676 2.2.2.6 PCON Register The Power Control (PCON) register contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Detect (BOD) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON Register bits are shown in Register 2-6. REGISTER 2-6: PCON — ...
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... Microchip Technology Inc. PIC16F630/676 2.3.2 STACK The PIC16F630/676 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...
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... Writing to the INDF register indirectly results operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-4. FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F630/676 Direct Addressing (1) From Opcode RP1 RP0 ...
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... MOVWF TRISA BCF STATUS,RP0 3.2 Additional Pin Functions Every PORTA pin on the PIC16F630/676 has an interrupt-on-change option and every PORTA pin, except RA3, has a weak pull-up option. The next two sections describe these functions. 3.2.1 WEAK PULL-UP Each of the PORTA pins, except RA3, has an individu- ally configurable weak internal pull-up ...
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... PIC16F630/676 REGISTER 3-2: TRISA — PORTA TRI-STATE REGISTER (ADDRESS: 85h) U-0 — bit 7 bit 7-6: Unimplemented: Read as ‘0’ bit 5-0: TRISA<5:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated PORTA pin configured as an output Note: TRISA<3> always reads 1. ...
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... Value at POR 2010 Microchip Technology Inc. U-0 R/W-0 R/W-0 R/W-0 — IOCA5 IOCA4 IOCA3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared PIC16F630/676 R/W-0 R/W-0 R/W-0 IOCA2 IOCA1 IOCA0 bit Bit is unknown DS40039F-page 23 ...
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... PIC16F630/676 3.2.3 PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individ- ual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet. ...
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... Figure 3-3 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset FIGURE 3-3: Data Bus RD TRISA PORTA Weak IOCA RD IOCA V DD Interrupt-on-Change I/O pin PIC16F630/676 RA3/MCLR/V PP BLOCK DIAGRAM OF RA3 MCLRE Reset I/O pin V SS MCLRE PORTA DS40039F-page 25 ...
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... PIC16F630/676 3.2.3.5 RA4/AN3/T1G/OSC2/CLKOUT Figure 3-4 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D (PIC16F676 only) • a TMR1 gate input • a crystal/resonator connection • a clock output ...
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... WPUA — — 96h IOCA — — Note 1: PIC16F676 only. Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. 2010 Microchip Technology Inc. PIC16F630/676 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RA5 RA4 RA3 RA2 RA1 ...
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... PIC16F630/676 3.3 PORTC PORTC is a general purpose I/O port consisting of 6 bidirectional pins. The pins can be configured for either digital I/O or analog input to A/D converter. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet. ...
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... Bit is cleared Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 ANS5 ANS4 ANS3 ANS2 PIC16F630/676 R/W-x R/W-x R/W-x RC2 RC1 RC0 bit Bit is unknown R/W-1 R/W-1 R/W-1 TRISC2 TRISC1 TRISC0 bit Bit is unknown Value on all ...
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... PIC16F630/676 NOTES: DS40039F-page 30 2010 Microchip Technology Inc. ...
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... The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut- off during Sleep 8-bit Prescaler PSA 8 1 PS0 - PS2 0 PSA PIC16F630/676 edge (T0SE) control bit ® Reference Manual, Data Bus 8 SYNC 2 TMR0 Cycles Set Flag bit T0IF ...
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... PIC16F630/676 4.3 Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore ...
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... RAPU INTEDG 85h TRISA — — Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. 2010 Microchip Technology Inc. PIC16F630/676 EXAMPLE 4-1: BCF STATUS,RP0 CLRWDT CLRF TMR0 BSF STATUS,RP0 MOVLW b’00101111’ ;Required if desired ...
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... PIC16F630/676 5.0 TIMER1 MODULE WITH GATE CONTROL The PIC16F630/676 devices have a 16-bit timer. Figure 5-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: • 16-bit timer/counter (TMR1H:TMR1L) • Readable and writable • Internal or external clock selection • ...
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... Timer1 Prescaler Timer1 has four prescaler options allowing divisions of the clock input. The T1CKPS bits (T1CON<5:4>) control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. PIC16F630/676 DS40039F-page 35 ...
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... PIC16F630/676 REGISTER 5-1: T1CON — TIMER1 CONTROL REGISTER (ADDRESS: 10h) U-0 R/W-0 — TMR1GE T1CKPS1 T1CKPS0 T1OSCEN bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0 This bit is ignored If TMR1ON = Timer1 T1G pin is low 0 = Timer1 is on bit 5-4 ...
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... Interrupt Service Routine on an overflow. Bit 5 Bit 4 Bit 3 Bit 2 T0IE INTE RAIE T0IF — — CMIF — — — CMIE — PIC16F630/676 time before use. Thus, Value on Value on Bit 1 Bit 0 all other POR, BOD Resets INTF RAIF 0000 0000 0000 000u — TMR1IF 00-- 0--0 00-- 0--0 ...
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... PIC16F630/676 NOTES: DS40039F-page 38 2010 Microchip Technology Inc. ...
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... COMPARATOR MODULE The PIC16F630/676 devices have one analog compar- ator. The inputs to the comparator are multiplexed with the RA0 and RA1 pins. There is an on-chip Comparator REGISTER 6-1: CMCON — COMPARATOR CONTROL REGISTER (ADDRESS: 19h) U-0 — COUT bit 7 bit 7 Unimplemented: Read as ‘ ...
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... PIC16F630/676 6.1 Comparator Operation A single comparator is shown in Figure 6-1, along with the relationship between the analog input levels and the digital output. When the analog input at V than the analog input V -, the output of the comparator digital low level. When the analog input at V ...
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... Multiplexed Input with Internal Reference and Output CM2:CM0 = 101 RA1/CIN- A COUT RA0/CIN+ A RA2/COUT D Multiplexed Input with Internal Reference CM2:CM0 = 110 RA1/CIN- A COUT RA0/CIN+ A RA2/COUT D PIC16F630/676 Off (Read as ‘0’) COUT From CV Module REF CIS = 0 CIS = 1 COUT From CV Module REF CIS = 0 CIS = 1 COUT From CV Module REF ...
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... PIC16F630/676 6.3 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 6-3. Since the analog pins are connected to a digital output, they have reverse biased diodes to V and V . The analog input, therefore, must be between SS V and the input voltage deviates from this ...
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... To minimize power consumption while in Sleep mode, turn off the comparator, CM2:CM0 = 111, and voltage refer- ence, VRCON<7> 2010 Microchip Technology Inc. PIC16F630/676 The following equations determine the output voltages: VRR = 1 (low range): CV VRR = 0 (high range ...
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... PIC16F630/676 REGISTER 6-2: VRCON — VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h) R/W-0 VREN bit 7 bit 7 VREN: CV REF circuit powered on REF circuit powered down REF bit 6 Unimplemented: Read as ‘0’ bit 5 VRR: CV Range Selection bit REF 1 = Low range 0 = High range bit 4 Unimplemented: Read as ‘0’ ...
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... RC bits For correct conversion, the A/D conversion clock (1/T ) must be selected to ensure a minimum T AD 1.6 s. Table 7-1 shows a few T selected frequencies. PIC16F630/676 pin. Figure 7-1 REF 10 10 ADRESH ADRESL is used analog voltage DD is used. The VCFG bit (ADCON0<6>) pin is the reference ...
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... PIC16F630/676 TABLE 7-1: T vs. DEVICE OPERATING FREQUENCIES AD A/D Clock Source ( Operation ADCS2:ADCS0 2 T 000 OSC 4 T 100 OSC 8 T 001 OSC 16 T 101 OSC 32 T 010 OSC 64 T 110 OSC A/D RC x11 Legend: Shaded cells are outside of recommended range. Note 1: The A/D RC source has a typical T 2: These values violate the minimum required T 3: For faster conversion times, the selection of another clock source is recommended ...
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... OSC 110 = F /64 OSC bit 3-0: Unimplemented: Read as ‘0’ Legend Readable bit - n = Value at POR 2010 Microchip Technology Inc. PIC16F630/676 U-0 R/W-0 R/W-0 R/W-0 — CHS2 CHS1 CHS0 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...
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... PIC16F630/676 REGISTER 7-3: ANSEL — ANALOG SELECT REGISTER (ADRESS: 91h) (PIC16F676 ONLY) R/W-1 R/W-1 ANS7 ANS6 bit 7 bit 7-0: ANS<7:0>: Analog Select between analog or digital function on pins AN<7:0>, respectively Analog input. Pin is assigned as analog input Digital I/O. Pin is assigned to port or special function. ...
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... PIC Mid-Range Reference Manual (DS33023). ) has no effect on the equation, since it cancels itself out not discharged after each conversion. HOLD V DD Sampling Switch LEAKAGE V = 0.6V T ± 500 PIC16F630/676 , see ACQ SS C HOLD = DAC capacitance = 120 Sampling Switch (k) DS40039F-page 49 ...
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... PIC16F630/676 7.3 A/D Operation During Sleep The A/D converter module can operate during Sleep. This requires the A/D clock source to be set to the internal oscillator. When the RC clock source is selected, the A/D waits one instruction before starting the conversion. This allows the SLEEP instruction to be executed, thus eliminating much of the switching noise from the conversion ...
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... EEDATA • EEADR EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. PIC16F630/676 devices have 128 bytes of data EEPROM with an address range from 0h to 7Fh. REGISTER 8-1: EEDAT — EEPROM DATA REGISTER (ADDRESS: 9Ah) ...
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... PIC16F630/676 8.1 EEADR The EEADR register can address maximum of 128 bytes of data EEPROM. Only seven of the eight bits in the register (EEADR<6:0>) are required. The MSb (bit 7) is ignored. The upper bit should always be ‘0’ to remain upward compatible with devices that have more data EEPROM memory ...
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... EEPROM. The WREN bit is not cleared by hardware. 2010 Microchip Technology Inc. PIC16F630/676 After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. ...
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... PIC16F630/676 8.7 DATA EEPROM OPERATION DURING CODE-PROTECT Data memory can be code-protected by programming the CPD bit to ‘0’. When the data memory is code-protected, the CPU is able to read and write data to the data EEPROM recommended to code-protect the program memory when code protecting data memory. This prevents ...
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... ID Locations • In-Circuit Serial Programming™ 2010 Microchip Technology Inc. PIC16F630/676 The PIC16F630/676 has a Watchdog Timer that is controlled by Configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable ...
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... LP oscillator: Low power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN Note 1: The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing the device as specified in the PIC16F630/676 Programming Specification. These bits are reflected in an export of the Configuration Word. Microchip Development Tools maintain all calibration bits to factory settings ...
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... Oscillator Configurations 9.2.1 OSCILLATOR TYPES The PIC16F630/676 can be operated in eight different Oscillator Option modes. The user can program three Configuration bits (FOSC2 through FOSC0) to select one of these eight modes: • LP Low-Power Crystal • XT Crystal/Resonator • HS High Speed Crystal/Resonator • RC External Resistor/Capacitor (2 modes) • ...
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... EXAMPLE 9-1: BSF CALL MOVWF BCF Internal Clock 9.2.6 CLKOUT The PIC16F630/676 devices can be configured to provide a clock out signal in the INTOSC and RC Oscillator modes. When configured, the oscillator frequency divided by four (F RA4/OSC2/CLKOUT pin. F purposes or to synchronize other logic. OSCILLATOR Z /4. OSC ...
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... Reset The PIC16F630/676 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during Sleep d) MCLR Reset during normal operation e) MCLR Reset during Sleep f) Brown-out Detect (BOD) Some registers are not affected in any Reset condition; ...
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... PIC16F630/676 9.3.1 MCLR PIC16F630/676 devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. ...
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... Then bringing MCLR high will begin execution immediately (see Figure 9-8). This is useful for testing purposes or to synchronize more than one PIC16F630/676 device operating in parallel. Table 9-6 shows the Reset conditions for some special registers, while Table 9-7 shows the Reset conditions for all the registers ...
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... PIC16F630/676 TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration PWRTE = 0 XT, HS PWRT 1024•T RC, EC, INTOSC T PWRT TABLE 9-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE POR BOD Legend unchanged unknown TABLE 9-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT Address Name Bit 7 Bit 6 03h STATUS ...
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... PIC16F630/676 • Wake-up from Sleep through interrupt • Wake-up from Sleep through WDT time-out uuuu uuuu — uuuu uuuu ( (4) uuuq quuu uuuu uuuu --uu uuuu ...
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... PIC16F630/676 FIGURE 9-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V ...
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... Interrupts The PIC16F630/676 has 7 sources of interrupt: • External Interrupt RA2/INT • TMR0 Overflow Interrupt • PORTA Change Interrupts • Comparator Interrupt • A/D Interrupt (PIC16F676 only) • TMR1 Overflow Interrupt • EEPROM Data Write Interrupt The Interrupt Control register (INTCON) and Peripheral Interrupt register (PIR) record individual interrupt requests in flag bits ...
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... PIC16F630/676 FIGURE 9-10: INTERRUPT LOGIC IOCA-RA0 IOCA0 IOCA-RA1 IOCA1 IOCA-RA2 IOCA2 IOCA-RA3 IOCA3 IOCA-RA4 IOCA4 IOCA-RA5 IOCA5 TMR1IF TMR1IE CMIF CMIE ADIF (1) ADIE EEIF EEIE Note 1: PIC16F676 only. DS40039F-page 66 T0IF Wake-up (If in Sleep mode) T0IE INTF INTE RAIF RAIE PEIE GIE ...
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... Module (PIC16F676 only)” for operation of the A/D converter interrupt. T0IE Interrupt Latency Inst ( — Dummy Cycle Inst (PC) . Synchronous latency = where PIC16F630/676 “Comparator Interrupts” for 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) Dummy Cycle = instruction cycle time. Latency CY DS40039F-page 67 ...
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... PIC16F630/676 TABLE 9-8: SUMMARY OF INTERRUPT REGISTERS Address Name Bit 7 Bit 6 0Bh, 8Bh INTCON GIE PEIE 0Ch PIR1 EEIF ADIF 8Ch PIE1 EEIE ADIE Legend unknown unchanged unimplemented read as ‘0’ value depends upon condition. Shaded cells are not used by the Interrupt module. ...
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... Address Name Bit 7 Bit 6 81h OPTION_REG RAPU INTEDG 2007h Config. bits CP BODEN MCLRE PWRTE WDTE Legend Unchanged, shaded cells are not used by the Watchdog Timer. 2010 Microchip Technology Inc. PIC16F630/676 1 0 8-bit Prescaler PSA 8 1 PS0 - PS2 0 PSA Bit 5 Bit 4 ...
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... PIC16F630/676 9.7 Power-Down Mode (Sleep) The Power-down mode is entered by executing a instruction. SLEEP If the Watchdog Timer is enabled: • WDT will be cleared but keeps running • PD bit in the STATUS register is cleared • TO bit is set • Oscillator driver is turned off • I/O ports maintain the status they had before ...
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... Program/Verify. Only the Least Significant 7 bits of the ID locations are used. 9.10 In-Circuit Serial Programming The PIC16F630/676 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for: • ...
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... PIC16F630/676 NOTES: DS40039F-page 72 2010 Microchip Technology Inc. ...
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... INSTRUCTION SET SUMMARY The PIC16F630/676 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction ...
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... PIC16F630/676 TABLE 10-2: PIC16F630/676 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 ...
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... Z Description: AND the W register with register ‘f’. If ‘d’ the result is stored in the W register. If ‘d’ the result is stored back in register ‘f’. 2010 Microchip Technology Inc. PIC16F630/676 BCF Bit Clear f Syntax: [label] BCF f,b 0 f 127 Operands: 0 ...
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... PIC16F630/676 CALL Call Subroutine Syntax: [ label ] CALL k 0 k 2047 Operands: Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Status Affected: None Description: Call Subroutine. First, return address ( pushed onto the stack. The eleven-bit immedi- ate address is loaded into PC bits < ...
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... Description: The contents of register ‘f’ are incremented. If ‘d’ the result is placed in the W register. If ‘d’ the result is placed back in register ‘f’. 2010 Microchip Technology Inc. PIC16F630/676 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d 0 f 127 Operands: d ...
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... PIC16F630/676 MOVF Move f Syntax: [ label ] MOVF f,d 0 f 127 Operands: d [0,1] (f) (destination) Operation: Status Affected: Z Description: The contents of register f are moved to a destination dependant upon the status destination is W register the destination is file register f itself useful to test a file register, since status flag Z is affected ...
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... Carry Flag. If ‘d’ the result is placed in the W register. If ‘d’ the result is placed back in register ‘f’. C Register f 2010 Microchip Technology Inc. PIC16F630/676 SLEEP Syntax: [ label ] SLEEP Operands: None 00h WDT, Operation: 0 ...
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... PIC16F630/676 SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d 0 f 127 Operands: d [0,1] (f<3:0>) (destination<7:4>), Operation: (f<7:4>) (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ the result is placed in the W register. If ‘ ...
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... Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. PIC16F630/676 ® DS40039F-page 81 ...
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... PIC16F630/676 11.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use ...
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... Programming™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. variable PIC16F630/676 ® Flash microcon- ® DSCs with the powerful, yet easy- ® ...
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... PIC16F630/676 11.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use inter- face for programming and debugging Microchip’s Flash families of microcontrollers. The ® Windows programming interface supports baseline (PIC10F, PIC12F5xx, ...
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... DD - DIS the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. should be used when applying a “low” level to the MCLR pin, rather than . SS PIC16F630/676 + 0.3V {( ( ...
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... PIC16F630/676 FIGURE 12-1: PIC16F630/676 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH, -40°C T +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 12-2: PIC16F676 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, -40°C T ...
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... FIGURE 12-3: PIC16F676 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 0°C T +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2.2 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2010 Microchip Technology Inc. PIC16F630/676 Frequency (MHz) 20 DS40039F-page 87 ...
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... PIC16F630/676 12.1 DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Supply Voltage DD D001 D001A D001B D001C D001D D002 V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 S V Rise Rate to ensure VDD ...
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... DC Characteristics: PIC16F630/676-I (Industrial) Param Device Characteristics No. D010 Supply Current ( D011 D012 D013 D014 D015 D016 D017 † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all I from rail-to-rail ...
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... PIC16F630/676 12.3 DC Characteristics: PIC16F630/676-I (Industrial) Param Device Characteristics No. D020 Power-down Base Current ( D021 D022 D023 D024 D025 D026 † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base I peripheral is enabled. The peripheral ...
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... DC Characteristics: PIC16F630/676-E (Extended) Param Device Characteristics No. D010E Supply Current ( D011E D012E D013E D014E D015E D016E D017E † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all I from rail-to-rail ...
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... PIC16F630/676 12.5 DC Characteristics: PIC16F630/676-E (Extended) Param Device Characteristics No. D020E Power-down Base Current ( D021E D022E D023E D024E D025E D026E † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base I peripheral is enabled. The peripheral ...
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... DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. Input Low Voltage V I/O ports IL D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (RC mode) D033 OSC1 (XT and LP modes) D033A OSC1 (HS mode) Input High Voltage V I/O ports ...
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... PIC16F630/676 12.7 DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended) (Cont.) DC CHARACTERISTICS Param Sym Characteristic No. Capacitive Loading Specs on Output Pins D100 C OSC2 pin OSC2 D101 C All I/O pins IO Data EEPROM Memory D120 E Byte Endurance D D120A E Byte Endurance D D121 V V for Read/Write DRW DD D122 T Erase/Write cycle time ...
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... High I Invalid (High-impedance) L Low FIGURE 12-4: LOAD CONDITIONS Load Condition 1 Pin Legend 464 for all pins for OSC2 output 2010 Microchip Technology Inc. T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z High-impedance Load Condition Pin V SS PIC16F630/676 DS40039F-page 95 ...
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... PIC16F630/676 12.9 AC CHARACTERISTICS: PIC16F630/676 (INDUSTRIAL, EXTENDED) FIGURE 12-5: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic No. F External CLKIN Frequency OSC Oscillator Frequency 1 T External CLKIN Period OSC (1) Oscillator Period Instruction Cycle Time 3 TosL, External CLKIN (OSC1) High ...
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... These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2010 Microchip Technology Inc. PIC16F630/676 Freq Min Typ† Max Units Tolerance ...
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... PIC16F630/676 FIGURE 12-6: CLKOUT AND I/O TIMING Q4 OSC1 CLKOUT I/O pin (Input) I/O pin Old Value (Output) TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym Characteristic No. 10 TosH2ckL OSC1 to CLOUT 11 TosH2ckH OSC1 to CLOUT 12 TckR CLKOUT rise time ...
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... Watchdog Timer Reset I/O Pins FIGURE 12-8: BROWN-OUT DETECT TIMING AND CHARACTERISTICS VDD (Device in Brown-out Detect) Reset (due to BOD) Note delay only if PWRTE bit in Configuration Word is programmed to ‘0’. 2010 Microchip Technology Inc. PIC16F630/676 (Device not in Brown-out Detect time-out 34 DS40039F-page 99 ...
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... PIC16F630/676 TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT DETECT REQUIREMENTS Param Sym Characteristic No MCLR Pulse Width (low Watchdog Timer Time-out WDT Period (No Prescaler Oscillation Start-up Timer OST Period 33* T Power-up Timer Period PWRT 34 T I/O High-impedance from ...
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... Microchip Technology Inc Min No Prescaler 0 With Prescaler 10 No Prescaler 0 With Prescaler 10 Greater Synchronous Greater of Asynchronous OSC PIC16F630/676 48 Typ† Max Units Conditions + 20 — — ns — — — — ns — — ns — — prescale value + 40 (2, 4, ..., 256 — — ns — — ns — — — ...
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... PIC16F630/676 TABLE 12-6: COMPARATOR SPECIFICATIONS Comparator Specifications Sym Characteristics V Input Offset Voltage OS V Input Common Mode Voltage CM C Common Mode Rejection Ratio MRR (1) T Response Time Comparator Mode Change Output Valid * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (V ...
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... DD V — REF — — 10 k A 10 — 1000 A — — pin, whichever is selected as reference input. REF DD PIC16F630/676 Conditions = 5.0V REF = 5.0V REF V = 5.0V REF = 5.0V REF = 5.0V REF V AIN REF Absolute minimum to ensure 10-bit accuracy During V acquisition ...
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... PIC16F630/676 FIGURE 12-10: PIC16F676 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 134 (T OSC Q4 A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 12-9: PIC16F676 A/D CONVERSION REQUIREMENTS ...
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... T AD s (Note 2) 11.5 — s 5* — — — — — OSC CY cycle. CY PIC16F630/676 NEW_DATA DONE Conditions 3.0V V REF V full range REF ADCS<1:0> (RC mode 2. 5.0V DD The minimum time is the amplifier settling time. This may be used if the “new” input voltage has not changed by more than 1 LSb (i ...
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... PIC16F630/676 NOTES: DS40039F-page 106 2010 Microchip Technology Inc. ...
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... Microchip Technology Inc. vs. V OVER TEMP (-40°C TO +25°C) DD Typical Baseline 3.5 4 4.5 V (V) DD vs. V OVER TEMP (+85°C) DD Typical Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD PIC16F630/676 DD - 5.5 85 5.0 5.5 DS40039F-page 107 ...
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... PIC16F630/676 FIGURE 13-3: TYPICAL I vs 4.0E-06 3.5E-06 3.0E-06 2.5E-06 2.0E-06 1.5E-06 1.0E-06 5.0E-07 0.0E+00 2.0 2.5 FIGURE 13-4: MAXIMUM I PD 1.0E-07 9.0E-08 8.0E-08 7.0E-08 6.0E-08 5.0E-08 4.0E-08 3.0E-08 2.0E-08 1.0E-08 0.0E+00 2 2.5 DS40039F-page 108 OVER TEMP (+125°C) DD Typical Baseline ...
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... Microchip Technology Inc. vs. V OVER TEMP (+85°C) DD Maximum Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (+125°C) DD Maximum Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD PIC16F630/676 85 5.0 5.5 125 5.0 5.5 DS40039F-page 109 ...
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... PIC16F630/676 FIGURE 13-7: TYPICAL I WITH BOD ENABLED vs 130 120 110 100 3.5 FIGURE 13-8: TYPICAL I WITH CMP ENABLED vs 1.8E-05 1.6E-05 1.4E-05 1.2E-05 1.0E-05 8.0E-06 6.0E-06 4.0E-06 2.0E-06 0.0E+00 2.0 2.5 DS40039F-page 110 OVER TEMP (-40°C TO +125°C) DD Typical BOD 4 (V) DD OVER TEMP (-40°C TO +125°C) ...
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... Microchip Technology Inc. WITH A/D ENABLED vs. V OVER TEMP (-40°C TO +25°C) DD Typical A 3.5 4 4.5 V (V) DD WITH A/D ENABLED vs. V OVER TEMP (+85°C) DD Typical A 3.5 4 4.5 V (V) DD PIC16F630/676 - 5 5.5 DS40039F-page 111 ...
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... PIC16F630/676 FIGURE 13-11: TYPICAL I WITH A/D ENABLED vs 3.5E-06 3.0E-06 2.5E-06 2.0E-06 1.5E-06 1.0E-06 5.0E-07 0.0E+00 2 2.5 FIGURE 13-12: TYPICAL I WITH T1 OSC ENABLED vs KHZ, C1 AND C2=50 pF) 1.20E-05 1.00E-05 8.00E-06 6.00E-06 4.00E-06 2.00E-06 0.00E+00 2.0 2.5 DS40039F-page 112 OVER TEMP (+125°C) DD Typical A/D I ...
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... Microchip Technology Inc. WITH CV ENABLED vs. V OVER TEMP (-40°C TO +125°C) REF DD Typical CV I REF PD 3 3.5 4 4.5 V (V) DD WITH WDT ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical WDT 3.5 4 4.5 V (V) DD PIC16F630/676 - 125 5 5.5 - 125 5 5.5 DS40039F-page 113 ...
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... PIC16F630/676 MAXIMUM AND MINIMUM INTOSC FREQ vs. TEMPERATURE WITH 0.1 F AND FIGURE 13-15: 0.01 F DECOUPLING (V 4.20E+06 4.15E+06 4.10E+06 4.05E+06 4.00E+06 3.95E+06 3.90E+06 3.85E+06 3.80E+06 -40°C MAXIMUM AND MINIMUM INTOSC FREQ vs. V FIGURE 13-16: DECOUPLING (+25°C) 4.20E+06 4.15E+06 4.10E+06 4 ...
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... FIGURE 13-17: TYPICAL WDT PERIOD vs 2.5 2010 Microchip Technology Inc. (-40 +125 WDT Time-out 3 3.5 4 4.5 V (V) DD PIC16F630/676 - 125 5 5.5 DS40039F-page 115 ...
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... PIC16F630/676 NOTES: DS40039F-page 116 2010 Microchip Technology Inc. ...
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... Note : In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2010 Microchip Technology Inc. PIC16F630/676 Example 16F630 1015/017 ...
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... PIC16F630/676 14.2 Package Details The following sections give the technical details of the packages. /HDG 3ODVWLF 'XDO ,Q/LQH 3 ± PLO %RG\ >3',3@ 1RWH N NOTE 1RWHV DS40039F-page 118 2010 Microchip Technology Inc. ...
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... PP %RG\ >62,&@ 1RWH N NOTE 1RWHV 2010 Microchip Technology Inc. PIC16F630/676 φ α c β DS40039F-page 119 ...
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... PIC16F630/676 1RWH DS40039F-page 120 2010 Microchip Technology Inc. ...
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... PP %RG\ >76623@ 1RWH NOTE 1RWHV 2010 Microchip Technology Inc. PIC16F630/676 φ L DS40039F-page 121 ...
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... PIC16F630/676 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40039F-page 122 2010 Microchip Technology Inc. ...
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... Revision F (05/2010) Replaced Package Drawings (Rev. BD); Replaced Development Support Section. 2010 Microchip Technology Inc. PIC16F630/676 APPENDIX B: DEVICE DIFFERENCES The differences between the PIC16F630/676 devices listed in this data sheet are shown in Table B-1. TABLE B-1: DEVICE DIFFERENCES Feature PIC16F630 A/D No DS40039F-page 123 ...
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... PIC16F630/676 APPENDIX C: DEVICE MIGRATIONS This section is intended to describe the functional and electrical specification differences when migrating between functionally similar devices (such as from a PIC16C74A to a PIC16C74B). Not Applicable DS40039F-page 124 APPENDIX D: MIGRATING FROM OTHER PIC DEVICES This discusses some of the issues in migrating from other PIC devices to the PIC16F6XX family of devices ...
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... Comparator ......................................................................... 39 Associated Registers .................................................. 44 Configuration............................................................... 41 Effects of a Reset........................................................ 43 I/O Operating Modes................................................... 41 Interrupts..................................................................... 44 Operation .................................................................... 40 Operation During Sleep .............................................. 43 2010 Microchip Technology Inc. PIC16F630/676 Output......................................................................... 42 Reference ................................................................... 43 Response Time .......................................................... 43 Comparator Specifications................................................ 102 Comparator Voltage Reference Specifications................. 102 Configuration Bits ............................................................... 56 Configuring the Voltage Reference..................................... 43 Crystal Operation................................................................ 57 Customer Change Notification Service ...
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... CMCON (Comparator Control) ................................... 39 CONFIG (Configuration Word) ................................... 56 EEADR (EEPROM Address) ...................................... 51 EECON1 (EEPROM Control) ..................................... 52 EEDAT (EEPROM Data) ............................................ 51 INTCON (Interrupt Control)......................................... 15 IOCA (Interrupt-on-Change PORTA).......................... 23 Maps PIC16F630 ......................................................... 10 PIC16F676 ......................................................... 10 OPTION_REG (Option) ........................................ 14, 32 OSCCAL (Oscillator Calibration) ................................ 18 PCON (Power Control) ............................................... 18 PIE1 (Peripheral Interrupt Enable 1)........................... 16 PIR1 (Peripheral Interrupt 1)....................................... 17 PORTC ....................................................................... 29 STATUS ...
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... DD Timer0 and Timer1 External Clock ........................... 101 Timer1 Incrementing Edge.......................................... 35 Timing Parameter Symbology............................................. 95 TRISIO Registers................................................................ 21 V Voltage Reference Accuracy/Error ..................................... 43 W Watchdog Timer Summary of Registers ................................................ 69 Watchdog Timer (WDT) ...................................................... 68 WWW Address.................................................................. 129 WWW, On-Line Support ....................................................... 5 2010 Microchip Technology Inc. PIC16F630/676 DS40039F-page 127 ...
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... PIC16F630/676 NOTES: DS40039F-page 128 2010 Microchip Technology Inc. ...
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... Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com PIC16F630/676 should contact their distributor, DS40039F-page 129 ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16F630/676 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
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... JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type. 2010 Microchip Technology Inc. PIC16F630/676 XXX Examples: Pattern a) PIC16F630 – E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 b) PIC16F676 package, 20 MHz – I/SL = Industrial Temp., SOIC DS40039F-page 131 ...
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... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 2010 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...