PIC16F630-I/SL Microchip Technology, PIC16F630-I/SL Datasheet - Page 12

IC MCU FLASH 1KX14 EEPROM 14SOIC

PIC16F630-I/SL

Manufacturer Part Number
PIC16F630-I/SL
Description
IC MCU FLASH 1KX14 EEPROM 14SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F630-I/SL

Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
RS- 232/USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Package
14SOIC N
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note 1:
Addr
PIC16F630/676
TABLE 2-2:
DS40039F-page 12
2:
3:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISC
PCLATH
INTCON
PIE1
PCON
OSCCAL
ANSEL
WPUA
IOCA
VRCON
EEDAT
EEADR
EECON1
EECON2
ADRESL
ADCON1
Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
IRP and RP1 bits are reserved, always maintain these bits clear.
PIC16F676 only.
Name
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
(3)
(3)
(3)
PIC16F630/676 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect data memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
EEPROM data register
EEPROM control register 2 (not a physical register)
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
Bit 7
RAPU
IRP
VREN
CAL5
ANS7
EEIE
GIE
(2)
EEPROM address register
INTEDG
ADCS2
RP1
Bit 6
ANS6
CAL4
PEIE
ADIE
(2)
TRISA5
TRISC5
WPUA5
ADCS1
IOCA5
Bit 5
ANS5
T0CS
CAL3
T0IE
VRR
RP0
Write buffer for upper 5 bits of program counter
TRISC4
WPUA4
TRISA4
ADCS0
IOCA4
Bit 4
T0SE
CAL2
ANS4
INTE
TO
WRERR
TRISA3
TRISC3
IOCA3
Bit 3
ANS3
CMIE
CAL1
RAIE
PSA
VR3
PD
TRISA2
TRISC2
WPUA2
IOCA2
WREN
Bit 2
CAL0
ANS2
T0IF
VR2
PS2
Z
TRISC1
WPUA1
TRISA1
IOCA1
Bit 1
ANS1
INTF
POR
PS1
VR1
WR
DC
 2010 Microchip Technology Inc.
TMR1IE
TRISA0
TRISC0
WPUA0
IOCA0
Bit 0
ANS0
RAIF
BOD
VR0
PS0
RD
C
Value on
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
--11 1111
--11 1111
---0 0000
0000 0000
00-- 0--0
---- --qq
1000 00--
1111 1111
--11 -111
--00 0000
0-0- 0000
0000 0000
0000 0000
---- x000
---- ----
xxxx xxxx
-000 ----
POR,
BOD
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