PIC16F627A-I/SO Microchip Technology, PIC16F627A-I/SO Datasheet - Page 107

• Manufacturer Part Number: PIC16F627A-I/SO
• Description: IC MCU FLASH 1KX14 EEPROM 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F627A-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILI3DBF648 - BOARD DAUGHTER ICEPIC3AC162053 - HEADER INTERFACE ICD,ICD2 18DIPAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.5.1
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION<6>) is set, or
falling, if INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the interrupt service
routine before re-enabling this interrupt. The RB0/INT
interrupt can wake-up the processor from Sleep, if the
INTE bit was set prior to going into Sleep. The status of
the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 14.8 "Power-Down Mode (Sleep)" for details
on Sleep, and Figure 14-17 for timing of wake-up from
Sleep through RB0/INT interrupt.
14.5.2
An overflow (FFh
set the T0IF (INTCON<2>) bit. The interrupt can
be
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0 "Timer0 Module".
FIGURE 14-15:
 2004 Microchip Technology Inc.
Note 1: INTF flag is sampled here (every Q1).
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
PC
Instruction
Fetched
Instruction
Executed
INSTRUCTION FLOW
enabled/disabled
2: Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time. Latency
3: CLKOUT is available in RC and INTOSC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
on
(3)
RB0/INT INTERRUPT
TMR0 INTERRUPT
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
the
Q1
Inst (PC-1)
RB0/INT
Inst (PC)
(1)
00h) in the TMR0 register will
INT PIN INTERRUPT TIMING
Q2
PC
by
(4)
Q3
setting/clearing
pin,
(5)
Q4
Q1
the
Inst (PC+1)
Inst (PC)
(1)
Q2
INTF
PC+1
Q3
T0IE
Preliminary
bit
Q4
PIC16F627A/628A/648A
Interrupt Latency
Q1
Dummy Cycle
Q2
14.5.3
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/disabled
by setting/clearing the RBIE (INTCON<4>) bit. For
operation of PORTB (Section 5.2 "PORTB and TRISB
Registers").
14.5.4
See
complete description of comparator interrupts.
PC+1
—
Note:
Q3
Section 10.6
Q4
(2)
If a change on the I/O pin should occur
when the read operation is being executed
(starts during the Q2 cycle and ends before
the start of the Q3 cycle), then the RBIF
interrupt flag may not get set.
PORTB INTERRUPT
COMPARATOR INTERRUPT
Q1
Dummy Cycle
Inst (0004h)
Q2
0004h
"Comparator
Q3
Q4
Q1
DS40044B-page 105
Interrupts"
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4
for