PIC16F627A-I/SO Microchip Technology, PIC16F627A-I/SO Datasheet - Page 59

• Manufacturer Part Number: PIC16F627A-I/SO
• Description: IC MCU FLASH 1KX14 EEPROM 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F627A-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILI3DBF648 - BOARD DAUGHTER ICEPIC3AC162053 - HEADER INTERFACE ICD,ICD2 18DIPAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.2.1
The user must configure the RB3/CCP1 pin as an
output by clearing the TRISB<3> bit.
9.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
TABLE 9-2:
 2004 Microchip Technology Inc.
0Bh, 8Bh,
10Bh, 18Bh
0Ch
8Ch
86h, 186h
0Eh
0Fh
10h
15h
16h
17h
Legend:
Address
Note:
Clearing the CCP1CON register will force
the RB3/CCP1 compare output latch to the
default low level. This is not the data latch.
CCP PIN CONFIGURATION
TIMER1 MODE SELECTION
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.
INTCON
PIR1
PIE1
TRISB
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
Name
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
PORTB Data Direction Register
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1register
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
Bit 7 Bit 6
EEIF CMIF
EEIE CMIE
GIE
—
—
PEIE
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCP1X
Bit 5
RCIE
RCIF
T0IE
CCP1Y
Bit 4
INTE
TXIF
TXIE
Preliminary
PIC16F627A/628A/648A
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Bit 3
RBIE
—
—
9.2.3
When generate software interrupt is chosen the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
9.2.4
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
CCP1IF
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
Bit 2
T0IF
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
TMR2IF
Bit 1
INTF
TMR1IF 0000 -000 0000 -000
Bit 0
RBIF
0000 000x 0000 000u
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on
POR
DS40044B-page 57
Value on
all other
Resets